Patents by Inventor John Steven Kuslak

John Steven Kuslak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7114063
    Abstract: A branch prediction method and system are provided that accurately predict a branch condition early in an instruction pipeline of a data processing system. By accurately predicting the branch condition, the correct target instruction can be fetched early, thereby avoiding many of the inefficiencies associated with branch mispredictions. To accurately predict if a branch condition is satisfied, one or more pre-calculated status bits are stored along with a digital value that is read by the conditional branch instruction to determine if the branch condition is satisfied. By including such a status bit, the condition of the conditional branch instruction may be immediately determined, without waiting for the instruction to be processed by an arithmetic unit or the like in a subsequent pipeline stage.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: September 26, 2006
    Assignee: Unisys Corporation
    Inventors: Lawrence Richard Fontaine, John Steven Kuslak, Gary John Lucas, Michael David Pelarski
  • Patent number: 6751756
    Abstract: A system and method for selectively injecting parity errors into instructions of a data processing system when the instructions are copied from a read buffer to a first level cache. The parity errors are selectively injected according to programmable indicators, each programmable indicator being associated with one or more instructions stored in the read buffer. The error-injection system also includes programmable operating modes whereby error injection will occur during, for example, every copy back from the read buffer to the first level cache, or alternatively, during only a selected copy back sequence. The system allows for comprehensive testing of error detection and recovery logic in an instruction processor, and further allows for comprehensive testing of the logic associated with performing a data re-fetch from a second level cache or storage device.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: June 15, 2004
    Assignee: Unisys Corporation
    Inventors: Thomas D. Hartnett, John Steven Kuslak, Douglas A. Fuller
  • Patent number: 5911083
    Abstract: A system and method for controlling the execution rate of an instruction processor on an instruction-by-instruction basis in a data processing system. The user controls the execution rate by specifying "cycle-slip" data for each instruction type in the instruction set. This cycle-slip data is used to force the instruction processor to idle for the specified number of execution cycles during the execution of the associated instruction type, thereby slowing down the rate of execution. Allowing rate control data to be unique for each instruction type allows temporary fixes to be implemented when timing-related hardware problems are discovered during system test. If desired, a uniform number of cycle slips can be imposed on all instructions so that the overall rate of the instruction processor is tailored to match the execution rate of slower peripheral devices.
    Type: Grant
    Filed: December 27, 1996
    Date of Patent: June 8, 1999
    Assignee: Unisys Corporation
    Inventor: John Steven Kuslak
  • Patent number: 5872910
    Abstract: A system and method for selectively injecting parity errors into instructions after the instructions are fetched from a storage device and are resident within the instruction processor in a data processing system. The parity errors are selectively injected according to programmable indicators, each programmable indicator being associated with one or more instructions stored in the storage device. The error-injection system also includes programmable operating modes whereby error injection will occur after every fetch of an associated instruction, or alternatively, after alternate fetches of an associated instruction. The system allows for comprehensive testing of error detection and recovery logic in an instruction processor, and further allows for comprehensive testing of the logic associated with performing a data re-fetch from the storage device.
    Type: Grant
    Filed: December 27, 1996
    Date of Patent: February 16, 1999
    Assignee: Unisys Corporation
    Inventors: John Steven Kuslak, Gary John Lucas, Nguyen Thai Tran