Patents by Inventor John Szeming Wang

John Szeming Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12592722
    Abstract: A method for generating soft information for a digital signal decoder. The method includes receiving a first plurality of signals, each corresponding to a time index, each time index being associated with two states including state 1 and state 0. The method also includes processing the first plurality of signals to calculate path metric values of state 0 and 1 for generating each of a second plurality of most-likely symbols by hard decisions and intermediate information for a most-likely path and a second-likely path at each time index. The method includes computing a difference between the most-likely path and a second-likely path for a given one of the two states at each time index. The method also includes determining a soft information corresponding to either one of the two states at the time index per one of the second plurality of most-likely symbols.
    Type: Grant
    Filed: May 1, 2024
    Date of Patent: March 31, 2026
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Haitao Xia, John Szeming Wang, Vasudevan Parthasarathy, Chung-Jue Chen, Sian She, Thomas V. Souvignier
  • Publication number: 20250343561
    Abstract: A method for generating soft information for a digital signal decoder. The method includes receiving a first plurality of signals, each corresponding to a time index, each time index being associated with two states including state 1 and state 0. The method also includes processing the first plurality of signals to calculate path metric values of state 0 and 1 for generating each of a second plurality of most-likely symbols by hard decisions and intermediate information for a most-likely path and a second-likely path at each time index. The method includes computing a difference between the most-likely path and a second-likely path for a given one of the two states at each time index. The method also includes determining a soft information corresponding to either one of the two states at the time index per one of the second plurality of most-likely symbols.
    Type: Application
    Filed: May 1, 2024
    Publication date: November 6, 2025
    Inventors: Haitao Xia, John Szeming Wang, Vasudevan Parthasarathy, Chung-Jue Chen, Sian She, Thomas V. Souvignier
  • Publication number: 20240396562
    Abstract: The systems and methods discussed herein related to digital to analog conversion. A digital to analog conversion a compensation circuit and a digital to analog conversion circuit. The compensation circuit includes a filter configured to provide roll off compensation in a baseband frequency using first coefficients. The compensation circuit is configured to convert the first digital signal to a second digital signal so that the second digital signal can be filtered by the filter using the first coefficients.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: John Szeming Wang, Kadir Dinc
  • Patent number: 12063048
    Abstract: The systems and methods discussed herein related to digital to analog conversion. A digital to analog conversion a compensation circuit and a digital to analog conversion circuit. The compensation circuit includes a filter configured to provide roll off compensation in a baseband frequency using real coefficients. The compensation circuit is configured to convert the first digital signal to a second digital signal so that the second digital signal can be filtered by the filter using the real coefficients.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: August 13, 2024
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: John Szeming Wang, Kadir Dinc
  • Patent number: 12010072
    Abstract: An apparatus includes an analog to digital converter configured to receive one or more first frames of a first component carrier signal having a first uplink-downlink subframe pattern, and receive one or more additional frames of at least one additional component carrier signal, the one more or more additional frames including one or more second frames of a second component carrier signal, the at least one additional component carrier signal including the second component carrier signal. The apparatus may further include control logic configured to activate timing skew calibration of at least one of the first or second component carrier signals based, at least in part, on an operating mode of the second component carrier signal and respective symbols of the first component carrier signal and second component carrier signal.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: June 11, 2024
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Jun Fang, John Szeming Wang, Sian She
  • Publication number: 20230299933
    Abstract: An apparatus includes an analog to digital converter configured to receive one or more first frames of a first component carrier signal having a first uplink-downlink subframe pattern, and receive one or more additional frames of at least one additional component carrier signal, the one more or more additional frames including one or more second frames of a second component carrier signal, the at least one additional component carrier signal including the second component carrier signal. The apparatus may further include control logic configured to activate timing skew calibration of at least one of the first or second component carrier signals based, at least in part, on an operating mode of the second component carrier signal and respective symbols of the first component carrier signal and second component carrier signal.
    Type: Application
    Filed: March 17, 2022
    Publication date: September 21, 2023
    Inventors: Jun Fang, John Szeming Wang, Sian She
  • Publication number: 20230138082
    Abstract: The systems and methods discussed herein related to digital to analog conversion. A digital to analog conversion a compensation circuit and a digital to analog conversion circuit. The compensation circuit includes a filter configured to provide roll off compensation in a baseband frequency using real coefficients. The compensation circuit is configured to convert the first digital signal to a second digital signal so that the second digital signal can be filtered by the filter using the real coefficients.
    Type: Application
    Filed: October 28, 2021
    Publication date: May 4, 2023
    Inventors: John Szeming Wang, Kadir Dinc
  • Publication number: 20160182156
    Abstract: A system includes an adjustable receiver a data line, a communications bus, and signal processing circuitry. The adjustable receiver may receive a signal and pass the received signal to the signal processing circuitry for data recovery and processing. For example, the adjustable receiver may detect an optical signal and pass the detected signal to signal processing circuitry for analog-to-digital conversion and digital processing. The signal processing circuitry may apply criteria to received signal to determine adjustment of selected parameters for the adjustable receiver. The signal processing circuitry may access addressable parameters in the adjustable receiver via the communications bus. By addressing the parameters the signal processing circuitry may apply the determined adjustments to the selected parameters in the adjustable receiver.
    Type: Application
    Filed: January 31, 2015
    Publication date: June 23, 2016
    Inventors: Frederick Sugihwo Tang, Vasudevan Parthasarathy, John Szeming Wang, Rajiv Pancholy