Patents by Inventor John T. Badar

John T. Badar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9483596
    Abstract: A method, system and computer program product for forming a netlist for an electronic circuit is disclosed. A Very High Speed Integrated Circuit Hardware Description Language (VHDL) file is created for a plurality of voltage domains. The VHDL file includes a voltage domain attribute and a logic voltage attribute for a pin of the electronic circuit. The voltage domain attribute and the logic voltage attribute for the pin are read from the VHDL file. Netlist instructions for the pin are synthesized to form a netlist for the electronic circuit. Synthesizing the netlist instructions begins with synthesizing netlist instructions within a voltage domain indicated by the voltage domain attribute and ends with synthesizing netlist instructions within a voltage domain indicated by the logic voltage attribute.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: November 1, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John T. Badar, David J. Geiger, KM Mozammel Hossain, Paul G. Villarrubia
  • Patent number: 8954914
    Abstract: A layout for an integrated circuit is designed by assigning physical design attributes including locations to a selected subset of placeable objects in the circuit netlist, prior to any physical synthesis. A layout abstract is displayed in a graphical user interface to allow the designer to visually inspect a layout abstract which shows the selected objects at their assigned locations. After making any desired modifications to the object locations, the location information can be formatted as a synthesis input file. Physical synthesis is then carried out while maintaining fixed locations for the selected objects according to the assigned locations. Physical design attributes can include coordinates and an orientation. The selected subset of placeable objects can constitute an identified datapath of the integrated circuit design.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: John T. Badar, David W. Lewis, Michael H. Wood, Matthew M. Ziegler
  • Publication number: 20140298278
    Abstract: A layout for an integrated circuit is designed by assigning physical design attributes including locations to a selected subset of placeable objects in the circuit netlist, prior to any physical synthesis. A layout abstract is displayed in a graphical user interface to allow the designer to visually inspect a layout abstract which shows the selected objects at their assigned locations. After making any desired modifications to the object locations, the location information can be formatted as a synthesis input file. Physical synthesis is then carried out while maintaining fixed locations for the selected objects according to the assigned locations. Physical design attributes can include coordinates and an orientation. The selected subset of placeable objects can constitute an identified datapath of the integrated circuit design.
    Type: Application
    Filed: April 2, 2013
    Publication date: October 2, 2014
    Applicant: International Business Machines Corporation
    Inventors: John T. Badar, David W. Lewis, Michael H. Wood, Matthew M. Ziegle