Abstract: The present invention is a system for efficiently generating test cases characterized by a linear range of integral values. A software testing tool which has been configured to generate test cases characterized by a linear range of integral values in accordance with the present invention can include a user interface coupled to a test case generator. The test case generator can be configured for range bounding for a range of integral values in a software application under test. In particular, the test case generator can include a halving module programmed to identify changes in response states in the software application under test evoked from input tokens having selected ones of the lengths defined within sub-ranges of a specified range of integral values.

Abstract: The present invention is a system for efficiently generating test cases characterized by a linear range of integral values. A software testing tool which has been configured to generate test cases characterized by a linear range of integral values in accordance with the present invention can include a user interface coupled to a test case generator. The test case generator can be configured for range bounding for a range of integral values in a software application under test. In particular, the test case generator can include a halving module programmed to identify changes in response states in the software application under test evoked from input tokens having selected ones of the lengths defined within sub-ranges of a specified range of integral values.

Abstract: A caching system and method are disclosed that allow for the caching of web pages that have dynamic content. The caching system and method utilize a cacheability analyzer that analyzes responses based on time, content, user identification, and macro hierarchy. The caching system only caches those responses having dynamic content that are deemed cacheable. Further, the automatic caching system can be overridden by the information author, the page creator or the system designer.

Abstract: A caching system and method are disclosed that allow for the caching of web pages that have dynamic content. The caching system and method utilize a cacheability analyzer that analyzes responses based on time, content, user identification, and macro hierarchy. The caching system only caches those responses having dynamic content that are deemed cacheable. Further, the automatic caching system can be overridden by the information author, the page creator or the system designer.

Abstract: A caching system and method are disclosed that allow for the caching of web pages that have dynamic content. The caching system and method utilize a cacheability analyzer that analyzes responses based on time, content, user identification, and macro hierarchy. The caching system only caches those responses having dynamic content that are deemed cacheable. The method for caching dynamic content includes identifying parts of a response to a request for dynamic content from a requestor and attributes associated with the parts. The attributes are examined to determine cacheability of the response. A cacheability is made based on the determination and the response may be cached based upon that cacheability determination.

Abstract: A data storage cell is provided for use when concatenated with similar cells in a wafer-scale integrated circuit as part of a serial memory chain. Data is stored in or retrieved from a shift register. A data switch is operable, dependently upon a selectable match criterion being met between the successive contents of a key word register and selectable sections of the data stored in register, the particular sections so selected being controlled by the contents of a control register. The access control is such that records are selectively stored in, or retrieved from, a particular cell dependent upon the content of the records themselves thus removing the necessity for keeping track of the position of records in the serial memory chain. The switch is selectably operable to provide a copy of the circulating contents of the data storage register as the signal on a data output line of the cell, so providing a means for non-destructive readout from the cell.

Abstract: A wafer-scale integrated circuit has a plurality of data-processing cells disposed on a semiconductor wafer together with a port for providing communications with a controller. A branched spiral of inter-coupled working cells is grown starting at the port by testing cells and incorporating them into the branched spiral if found to be working, otherwise selecting alternative cells for testing. The growth of the branched spiral is such as to allow for the incorporation of cells trapped in cul-de-sacs. Each cell is operable to receive a unique cell name from the controller and is thereafter operable to respond to commands from the controller bearing its unique cell name to couple firstly to one neighbor and secondly, at any time thereafter, to couple to a further neighboring cell. The controller is provided with means for maintaining records of successful interconnections for later use.

Abstract: A very large scale integrated circuit, covering the entire surface of a semiconductor wafer, comprises a plurality of data processing cells and a port. Starting at the port, cells can be made to couple to neighboring cells which are then tested and incorporated into the overall working of the integrated circuit if functional to grow a functional array of interconnected cells on the wafer.Each cell is square and comprises a data processing element, four coupling sections and four link sections. The link sections allow the cell either to communicate with one of its four neighbors or to internally circulate data. The coupling sections join the link sections. The data processing element is associated with one of the link sections. The cells are divided into two groups, a first group with its cells all having the element associated with the coupling section in one corner and a second group with its cells all having the element associated with the coupling section in the opposite corner.

Abstract: A memory system includes an integrated circuit comprising a plurality of testably interconnectable cells in a tessellation on a semiconducting wafer. A controller for acting as an interface between the wafer and some host system is coupled to the wafer via a port formed by the omission of one of the cells from the tessellation. Each cell comprises plural-bit data storage registers each having an associated single-bit access register and an associated single-bit control register. During a growth phase a state machine co-operates with global signals and test data from the controller to operate data-testing and inter-register coupling logic to form a branched-labyrinth of tested cells characterized by rapid growth and efficient incorporation of functional cells. After growth data is transferred between the chain of data storage registers and the chain of access registers so formed dependently upon the contents of an associated chain of control registers.