Patents by Inventor John T. Contreras

John T. Contreras has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105217
    Abstract: Various illustrative aspects are directed to a data storage device comprising a storage medium and a head configured to access the storage medium. The head comprises a first write assist element and a second write assist element. Control circuitry for driving the head is configured to apply a first write assist current Im that is synchronized to a write data current Iw to the first write assist element; and to apply a second DC write assist current Imdc to the second write assist element.
    Type: Application
    Filed: September 14, 2023
    Publication date: March 28, 2024
    Inventors: Joey M. Poss, Yunfei Ding, John T. Contreras
  • Publication number: 20240097696
    Abstract: Example channel circuits, data storage devices, and methods for asynchronous sampling from an oversampled analog-to-digital converter are described. The channel circuit may include an analog-to-digital converter configured to generate an oversampled digital signal from an analog data signal using a sample rate that is an integer multiple of the baud rate of the channel circuit. A digital sample interpolator may then interpolate interpolated digital signal values from multiple signal values of the oversampled digital signal and select values at baud rate to generate a baud rate digital signal. The baud rate digital signal may be used by an iterative detector in a timing loop and, once a target timing is achieved, for the iterative detector to detect data bits from the interpolated digital signal.
    Type: Application
    Filed: July 18, 2023
    Publication date: March 21, 2024
    Inventors: Richard Galbraith, Michael J. Ross, Weldon M. Hanson, John T. Contreras, Iouri Oboukhov, Niranjay Ravindran, Pradhan Bellam, Derrick E. Burton
  • Patent number: 11615804
    Abstract: A data storage device is disclosed comprising a storage medium and a head configured to access the storage medium, wherein the head comprises a first write assist element (WA1) comprising a first terminal and a second terminal and a second write assist element (WA2) comprising a first terminal and a second terminal. The second terminal of the WA1 and the second terminal of the WA2 are coupled together to form a common node. A first bias signal is applied to the first terminal of the WA1, a second bias signal is applied to the first terminal of the WA2, and a common mode voltage is applied to the common node.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: March 28, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Joey M. Poss, John T. Contreras, Ian Robson McFadyen, Yaw Shing Tang
  • Patent number: 11362063
    Abstract: A semiconductor device is disclosed including a wire bonded die stack where the bond wires skip dies in the die stack to provide bond wires having a long length. In one example, the semiconductor dies are stacked on top of each other with offsets along two orthogonal axes so that the dies include odd numbered dies interspersed and staggered with respect to even numbered dies only one of the axes. Wire bonds may be formed between the odd numbered dies, skipping the even numbered dies, and wire bonds may be formed between the even numbered dies, skipping the odd numbered dies. The long length of the bond wires increases an inductance of the wire bonds relative to parasitic capacitance of the semiconductor dies, thereby increasing signal path bandwidth of the semiconductor device.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 14, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Xinzhi Xing, John T. Contreras
  • Patent number: 11361786
    Abstract: A data storage device is disclosed comprising a head actuated over a magnetic media, wherein the head comprises a read element configured to generate a read signal when reading data from the magnetic media. A common-source common-gate (CS-CG) differential amplifier is coupled to the read element through a transmission line having a transmission line impedance Z0. A feedback circuit is coupled between an output of the CS-CG differential amplifier and an input of the CS-CG differential amplifier, wherein the feedback circuit is configured so that an input impedance of the CS-CG differential amplifier substantially matches the transmission line impedance Z0.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: June 14, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: John T. Contreras, Joey M. Poss
  • Publication number: 20220165299
    Abstract: A data storage device is disclosed comprising a head actuated over a magnetic media, wherein the head comprises a read element configured to generate a read signal when reading data from the magnetic media. A common-source common-gate (CS-CG) differential amplifier is coupled to the read element through a transmission line having a transmission line impedance Z0. A feedback circuit is coupled between an output of the CS-CG differential amplifier and an input of the CS-CG differential amplifier, wherein the feedback circuit is configured so that an input impedance of the CS-CG differential amplifier substantially matches the transmission line impedance Z0.
    Type: Application
    Filed: February 22, 2021
    Publication date: May 26, 2022
    Inventors: John T. Contreras, Joey M. Poss
  • Patent number: 11295764
    Abstract: A data storage device is disclosed comprising a head actuated over a magnetic media, wherein the head comprises a write element and a first read element. A preamp circuit comprising an interface includes at least a write line associated with the write element of the head and a first read line associated with the first read element of the head. A first read signal is received from the preamp circuit over the first read line during a read operation, and configuration data is transmitted to the preamp circuit over the first read line during a write operation.
    Type: Grant
    Filed: March 28, 2021
    Date of Patent: April 5, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Jonas A. Goode, Richard L. Galbraith, Joey M. Poss, John T. Contreras
  • Patent number: 10950265
    Abstract: A method of operating a data storage device is disclosed comprising an enclosure comprising a first head actuated over a first disk surface and a second head actuated over a second disk surface. A manufacture printed circuit board (PCB) is coupled to the enclosure, wherein the manufacture PCB comprises at least one dual channel configured to execute concurrent access operations. While the manufacture PCB is coupled to the enclosure, the data storage device is operated as a dual channel device. The manufacture PCB is decoupled from the enclosure and a product PCB is coupled to the enclosure, wherein the product PCB comprises a single channel configured to execute a single access operation.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: March 16, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Junzo Noda, John T. Contreras, Robert C. Reinhart, Michael J. Esmond, Masahito Kobayashi, Alec Parken
  • Patent number: 10896695
    Abstract: A data storage device is disclosed comprising a top head actuated over a top surface of a first disk, a bottom head actuated over a bottom surface of the first disk, a top head actuated over a top surface of a second disk, and a bottom head actuated over a bottom surface of the second disk. A dual channel preamp circuit is coupled to the top and bottom heads of the first and second disks, wherein a selection signal is applied to the dual channel preamp circuit to select between the first disk and the second disk. A concurrent access operation of the top and bottom surface of the selected disk is executed using the dual channel preamp circuit.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: January 19, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Junzo Noda, John T. Contreras, Masahito Kobayashi
  • Publication number: 20200098728
    Abstract: A semiconductor device is disclosed including a wire bonded die stack where the bond wires skip dies in the die stack to provide bond wires having a long length. In one example, the semiconductor dies are stacked on top of each other with offsets along two orthogonal axes so that the dies include odd numbered dies interspersed and staggered with respect to even numbered dies only one of the axes. Wire bonds may be formed between the odd numbered dies, skipping the even numbered dies, and wire bonds may be formed between the even numbered dies, skipping the odd numbered dies. The long length of the bond wires increases an inductance of the wire bonds relative to parasitic capacitance of the semiconductor dies, thereby increasing signal path bandwidth of the semiconductor device.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Xinzhi Xing, John T. Contreras
  • Patent number: 10564053
    Abstract: Embodiments disclosed herein generally relate to a method for monitoring optical power in a HAMR device. In one embodiment, the method includes enhancing a thermal sensor bandwidth through advanced electrical detection techniques. The advanced electrical detection techniques include obtaining calibration waveform data for a thermal sensor by calibrating the thermal sensor, obtaining real-time waveform data for the thermal sensor that may deviate from the calibration waveform data, updating the calibration waveform data to include the real-time waveform data, repeating obtaining real-time waveform data and updating the calibration waveform data during writing operations. By updating the calibration waveform data, the bandwidth of the thermal sensor is determined by a fixed sampling time interval, and the thermal sensor rise time to steady state would not be a limitation to its response time.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: February 18, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: John T. Contreras, Lidu Huang, Shen Ren, Erhard Schreck, Rehan Ahmed Zakai
  • Publication number: 20190120705
    Abstract: Embodiments disclosed herein generally relate to a method for monitoring optical power in a HAMR device. In one embodiment, the method includes enhancing a thermal sensor bandwidth through advanced electrical detection techniques. The advanced electrical detection techniques include obtaining calibration waveform data for a thermal sensor by calibrating the thermal sensor, obtaining real-time waveform data for the thermal sensor that may deviate from the calibration waveform data, updating the calibration waveform data to include the real-time waveform data, repeating obtaining real-time waveform data and updating the calibration waveform data during writing operations. By updating the calibration waveform data, the bandwidth of the thermal sensor is determined by a fixed sampling time interval, and the thermal sensor rise time to steady state would not be a limitation to its response time.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 25, 2019
    Inventors: John T. CONTRERAS, Lidu HUANG, Shen REN, Erhard SCHRECK, Rehan Ahmed ZAKAI
  • Patent number: 10175122
    Abstract: Embodiments disclosed herein generally relate to a method for monitoring optical power in a HAMR device. In one embodiment, the method includes enhancing a thermal sensor bandwidth through advanced electrical detection techniques. The advanced electrical detection techniques include obtaining calibration waveform data for a thermal sensor by calibrating the thermal sensor, obtaining real-time waveform data for the thermal sensor that may deviate from the calibration waveform data, updating the calibration waveform data to include the real-time waveform data, repeating obtaining real-time waveform data and updating the calibration waveform data during writing operations. By updating the calibration waveform data, the bandwidth of the thermal sensor is determined by a fixed sampling time interval, and the thermal sensor rise time to steady state would not be a limitation to its response time.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: January 8, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: John T. Contreras, Lidu Huang, Shen Ren, Erhard Schreck, Rehan A. Zakai
  • Patent number: 10056098
    Abstract: A data storage device is disclosed comprising a head actuated over a disk, wherein the head comprises a first sensor element and a second sensor element. When configured into a first single-ended mode, a bias signal is applied to the first sensor element to generate a first single-ended output signal based on a response of the first sensor element, and when configured into a second single-ended mode, the bias signal is applied to the second sensor element to generate a second single-ended output signal based on a response of the first sensor element. When configured into a differential mode, the bias signal is concurrently applied to the first sensor element and the second sensor element to generate a differential output signal based on a response of the first sensor element and the second sensor element.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: August 21, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sukumar Rajauria, Erhard Schreck, John T. Contreras, Joey M. Poss, Rehan A. Zakai, Robert Smith, Barry C. Stipe
  • Publication number: 20170336271
    Abstract: Embodiments disclosed herein generally relate to a method for monitoring optical power in a HAMR device. In one embodiment, the method includes enhancing a thermal sensor bandwidth through advanced electrical detection techniques. The advanced electrical detection techniques include obtaining calibration waveform data for a thermal sensor by calibrating the thermal sensor, obtaining real-time waveform data for the thermal sensor that may deviate from the calibration waveform data, updating the calibration waveform data to include the real-time waveform data, repeating obtaining real-time waveform data and updating the calibration waveform data during writing operations. By updating the calibration waveform data, the bandwidth of the thermal sensor is determined by a fixed sampling time interval, and the thermal sensor rise time to steady state would not be a limitation to its response time.
    Type: Application
    Filed: May 20, 2016
    Publication date: November 23, 2017
    Inventors: John T. CONTRERAS, Lidu HUANG, Shen REN, Erhard SCHRECK, Rehan A. ZAKAI
  • Patent number: 9717140
    Abstract: The present disclosure generally relates to a shielded patterned ground structure in a PCB. The PCB may be disposed in a hard disk drive. Conductive traces in PCBs can have the problem of common mode current flowing through the traces and thus increasing the magnitude of EMI noise. By providing a shielded patterned ground structure, the common mode current is reduced as is the magnitude of EMI noise, yet there is no negative impact to the differential signal.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: July 25, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventors: John T. Contreras, Junjia Liu, Satoshi Nakamura, Jack Nguyen, Albert John Wallash
  • Publication number: 20170127509
    Abstract: The present disclosure generally relates to a shielded patterned ground structure in a PCB. The PCB may be disposed in a hard disk drive. Conductive traces in PCBs can have the problem of common mode current flowing through the traces and thus increasing the magnitude of EMI noise. By providing a shielded patterned ground structure, the common mode current is reduced as is the magnitude of EMI noise, yet there is no negative impact to the differential signal.
    Type: Application
    Filed: October 29, 2015
    Publication date: May 4, 2017
    Inventors: John T. CONTRERAS, Junjia LIU, Satoshi NAKAMURA, Jack NGUYEN, Albert John WALLASH
  • Publication number: 20150380027
    Abstract: Embodiments described herein generally relate to resistive shunt design in a read sensor for providing accurate measurements from an electronic lapping guide (ELG). More specifically, embodiments described herein relate to a transducer resistor shunt structure for low cost probing. A bleed resistor network for a read sensor may comprise one or more first resistors arranged in parallel with one another and a second resistor arranged in series with the one or more first resistors. The resistor arrangement may require a small physical area and reduce or prevent ELG measurement errors.
    Type: Application
    Filed: September 4, 2015
    Publication date: December 31, 2015
    Inventors: John T. CONTRERAS, David Patrick DRUIST, Edward Hin Pong LEE, David J. SEAGLE, Darrick Taylor SMITH
  • Patent number: 9129660
    Abstract: Embodiments described herein generally relate to resistive shunt design in a read sensor for providing accurate measurements from an electronic lapping guide (ELG). More specifically, embodiments described herein relate to a transducer resistor shunt structure for low cost probing. A bleed resistor network for a read sensor may comprise one or more first resistors arranged in parallel with one another and a second resistor arranged in series with the one or more first resistors. The resistor arrangement may require a small physical area and reduce or prevent ELG measurement errors.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: September 8, 2015
    Assignee: HGST NETHERLANDS B.V.
    Inventors: John T. Contreras, David Patrick Druist, Edward Hin Pong Lee, David John Seagle, Darrick Taylor Smith
  • Publication number: 20150154992
    Abstract: Embodiments described herein generally relate to resistive shunt design in a read sensor for providing accurate measurements from an electronic lapping guide (ELG). More specifically, embodiments described herein relate to a transducer resistor shunt structure for low cost probing. A bleed resistor network for a read sensor may comprise one or more first resistors arranged in parallel with one another and a second resistor arranged in series with the one or more first resistors. The resistor arrangement may require a small physical area and reduce or prevent ELG measurement errors.
    Type: Application
    Filed: December 4, 2013
    Publication date: June 4, 2015
    Applicant: HGST NETHERLANDS B.V.
    Inventors: John T. CONTRERAS, David Patrick DRUIST, Edward Hin Pong LEE, David John SEAGLE, Darrick Taylor SMITH