Patents by Inventor John T. Gehman

John T. Gehman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4443848
    Abstract: A digital processor including both macro and micro instruction generators. The micro-instruction generator comprises a sequencer for generating instruction addresses, a memory for generating instructions in response to the addresses and a pipeline register adapted to receive the instructions for execution. The sequencer operates at a constant CLK 1 rate while the pipeline register operates at a variable CLK 2 rate; i.e., the occurrence of a branch instruction in the pipeline register operates to inhibit CLK 2 for one CLK 1 time so as to prevent loading for execution of the aborted sequential instruction during the loading of a new non-sequential instruction address. CLK 2 resumes upon the next CLK 1 signal to resume sequential operation. Special branch instructions are utilized to fetch macro-instructions from a pipelined system of macro-instruction registers. A two-tier synchronous arbitration system for memory requests is also disclosed.
    Type: Grant
    Filed: May 4, 1981
    Date of Patent: April 17, 1984
    Assignee: Nixdorf Computer Corporation
    Inventor: John T. Gehman
  • Patent number: 4310880
    Abstract: A digital processor including both macro and micro instruction generators. The micro-instruction generator comprises a sequencer for generating instruction addresses, a memory for generating instructions in response to the addresses and a pipeline register adapted to receive the instructions for execution. The sequencer operates at a constant CLK 1 rate while the pipeline register operates at a variable CLK 2 rate; i.e., the occurrence of a branch instruction in the pipeline register operates to inhibit CLK 2 for one CLK 1 time so as to prevent loading for execution of the aborted sequential instruction during the loading of a new non-sequential instruction address. CLK 2 resumes upon the next CLK 1 signal to resume sequential operation. Special branch instructions are utilized to fetch macro-instructions from a pipelined system of macro-instruction registers. A two-tier synchronous arbitration system for memory requests is also disclosed.
    Type: Grant
    Filed: September 10, 1979
    Date of Patent: January 12, 1982
    Assignee: Nixdorf Computer Corporation
    Inventor: John T. Gehman