Abstract: A computer-implemented method may include determining that a slot coupled to a peripheral component interconnect host bridge is occupied by an input/output adapter. The computer-implemented method may include determining one or more characteristics of the input/output adapter and determining whether the input/output adapter is capable of using additional memory based on the one or more characteristics of the input/output adapter. The computer-implemented method may also include allocating the additional memory for the input/output adapter in response to determining that the input/output adapter is capable of using the additional memory.

Abstract: A computer-implemented method may include determining that a slot coupled to a peripheral component interconnect host bridge is occupied by an input/output adapter. The computer-implemented method may include determining one or more characteristics of the input/output adapter and determining whether the input/output adapter is capable of using additional memory based on the one or more characteristics of the input/output adapter. The computer-implemented method may also include allocating the additional memory for the input/output adapter in response to determining that the input/output adapter is capable of using the additional memory.

Abstract: In response to a hypervisor page fault for memory that is not resident in a shared memory pool, an I/O paging request is sent to an external storage paging space. In response to a paging service partition encountering an I/O paging error, a paging failure indication is sent to the hypervisor. A simulated machine check interrupt instruction is sent from the hypervisor to the shared memory partition and a machine check handler obtains control. The machine check handler performs data analysis utilizing an error log in an attempt to isolate the I/O paging error to a process or a set of processes in the shared memory partition. The process or set of processes associated with the I/O paging error, or the shared memory partition itself, may be terminated. Finally, the shared memory partition may clear or initialize the page associated with the I/O paging error.

Abstract: A method and system that enable system firmware to efficiently boot an operating system (OS) and/or client program from a network-connected Internet Small Computer Systems Interface (iSCSI) device. The method generally comprises: (1) defining the firmware representation of the iSCSI device within the hierarchical data structure that represents the system hardware; and (2) extending the network support package to accommodate additional boot arguments that allow system firmware to acquire the information required for booting from the network-connected iSCSI device, while utilizing one of the existing discovery protocols.

Abstract: A method and system for selecting the architecture level to which a processor appears to conform within a computing environment when executing specific logical partitions or programs and performing migration among different levels of processor architecture. The method utilizes a “processor compatibility register” (PCR) that controls the level of the architecture that the processor appears to support. In one embodiment, the PCR is accessible only to super-privileged software. The super-privileged software sets bits in the PCR that specify the architecture level that the processor is to appear to support so that when the program runs on the processor, the processor behaves in accordance with the architecture level for which the program was designed.

Abstract: A mechanism is added to a network support package to enable/allow the specification of additional boot discovery protocols and additional network address formats. The mechanism defines qualifier keywords that are added to the boot arguments and processed by the network support package. The qualifier keywords modify the boot arguments associated with a bootstrap method by specifying a way to acquire the arguments (i.e., a specific boot discovery protocol), the format of the arguments, and other parameters associated with the arguments. Multiple qualifier keywords may be added to the boot arguments at a time, and the keywords can be applied in their order within the arguments.

Abstract: Firmware of an InfiniBand (IB) host computer device provides a representation of an IB Host Channel Adapter (HCA) within the hierarchical data structure during system initialization. An ib-boot support package encapsulates arguments for booting over an IB network using an ibport device. The ib-boot support package supports use of one or more command keywords, each identifying a specific type of support package utilized to retrieve the boot image. When the srp keyword is provided, an SRP protocol is used to access the storage boot device and retrieve the boot file. Access to the boot server is thus provided via one of the support packages, and the boot image is returned to the host device via the IB network for completion of boot operations.

Abstract: Firmware of an InfiniBand (IB) host computer device provides a representation of an IB Host Channel Adapter (HCA) within the hierarchical data structure during system initialization. An ib-boot support package encapsulates arguments for booting over an IB network using an ibport device. The ib-boot support package supports keywords identifying a network support package or a Sockets Direct Protocol (SDP) support package. When the first keyword is provided, the IPoIB network protocol is used to access the boot server and retrieve the boot file. When the second keyword is provided, the IB network boot method is implemented, whereby the SDP network protocol is used to access the boot device. Access to the boot server is thus provided via one of the support packages, and the boot image is returned to the host device via the IB network for completion of boot operations.

Abstract: In response to a hypervisor page fault for memory that is not resident in a shared memory pool, an I/O paging request is sent to an external storage paging space. In response to a paging service partition encountering an I/O paging error, a paging failure indication is sent to the hypervisor. A simulated machine check interrupt instruction is sent from the hypervisor to the shared memory partition and a machine check handler obtains control. The machine check handler performs data analysis utilizing an error log in an attempt to isolate the I/O paging error to a process or a set of processes in the shared memory partition. The process or set of processes associated with the I/O paging error, or the shared memory partition itself, may be terminated. Finally, the shared memory partition may clear or initialize the page associated with the I/O paging error.

Abstract: A method and apparatus for improving data processing system performance having a cache. Data from one cache line is easily and quickly copied to another cache line within the cache. In the preferred embodiment, this copy cache line operation is initiated using an opcode of a central processing unit's instruction set. Thus, software running on the data processing system can invoke this cache line copy by executing this CPU instruction.Another feature is the ability to rename a cache line, again using a CPU instruction to initiate the operation. This provides a logical copy of the cache data without having to perform a physical copy.

Abstract: A cache for use with input/output devices attached to an input/output bus. Requests for access to system memory by an input/output device pass through the cache. Access authority is checked to determine whether an input/output device is authorized to access that particular page. If it is not, access is denied. Each input/output device has access to a portion of the cache, so that activity by one device will not interfere with activity by another.

Abstract: A computer system has a cache located between input/output devices and a main system memory. All system memory accesses by the input/output devices are made through the cache. Memory accesses through the cache are limited to those addresses which are accessible to a central processor and input/output devices. All access to such addresses by the central processor are made through the cache.

Abstract: A computer system has a cache located between input/output devices and a main system memory. All system memory accesses by the input/output devices are made through the cache. Memory accesses through the cache are limited to those addresses which are accessible to a central processor and input/output devices. All access to such addresses by the central processor are made through the cache.

Abstract: A data processing method for storing groups of related information in a storage subsystem of a data processing system in which the storage subsystem includes one or more storage devices having a plurality of block addressable storage locations (blocks or sectors) each of which stores a predetermined fixed number of bytes of said information. The method includes the step of establishing allocatable increments of storage, called physical partitions, which comprise a predetermined number of contiguous addressable blocks, and initially allocating, in response to a request to the operating system, a preselected number of partitions for each group of related information, where the partitions in each group are not necessarily physically contiguous and where the number that is selected is the minimum number of partitions required to store the group of related information.

Abstract: A method for use in a virtual memory data processing system employing a pageable External Page Table data structure for recording current status and disk address information for each virtual page in said system, provides improved system performance when a large number of virtual pages are to be operated on in the same manner. In accordance with the method, each page of External Page Table entries can record a predetermined number of entries (512), depending on the byte capacity of each virtual page (2,048) and the size of each entry (4 bytes). One page of 512 entries correspond to 1 megabyte of virtual storage (512.times.2,048) and also appears as one entry in a pinned External Page Table. The pinned External Page Table is referred to as the "XPT of the XPT," and has the same format as the pageable XPT. A 256 megabyte segment of virtual memory is representable in the XPT of the XPT by 256, 4 byte entries, or one-half of a page.

Abstract: A method to logically serialize a plurality of independent system events in a virtual memory data processing system. Each event causes interrupt servicing routines to be executed and requires data structures that record the status of virtual pages to be updated. The system events include the interrupt that is generated as a result of a page fault, the interrupt that is generated as a result of a paging I/O completion operation that resolves a page fault, and lastly interrupts generated in response to a supervisory call to a paging service.

Abstract: A system for diagnosing and correcting errors in remote data processing equipment is provided in which a remote data processor subject to an error condition has associated therewith disk, e.g., diskette storage means together with means for recording on said diskettes, data representing the status of the data processor under a particular error condition. The remote data processor further has associated therewith means for transmitting the status data stored on said diskette. First receiving means distant from the remote data processor receives the transmitted data and means associated with the receiving means reconstruct the diskette containing the error status data whereby this reconstruct diskette is now available for diagnostics at a point distant from said remote data processor.

Abstract: A method to logically serialize a plurality of independent system events in a virtual memory data processing system. Each event causes interrupt servicing routines to be executed and requires data structures that record the status of virtual pages to be updated. The system events include the interrupt that is generated as a result of a page fault, the interrupt that is generated as a result of a paging I/O completion operation that resolves a page fault, and lastly interrupts generated in response to a supervisory call to a paging service.