Abstract: A rotor assembly for a peristaltic pump is provided. Each of a first pair of roller assemblies includes a first roller portion having a first diameter and a second roller portion having a second diameter. The first diameter is larger than the second diameter. Each of a second pair of roller assemblies includes a first roller portion having a first diameter and a second roller portion having a second diameter. The first diameter is smaller than the second diameter. The first and second pairs of roller assemblies are positionable around a circumference of a hub such that the first roller portion of the first pair of roller assemblies is aligned with the first roller portion of the second pair of roller assemblies and the second roller portion of the first pair of roller assemblies is aligned with the second roller portion of the second pair of roller assemblies.

Abstract: A DLL system in a memory device with wide frequency application includes: a clock receiver that generates a clock for the DLL system; a delay line, coupled to the clock receiver, for receiving the generated clock and delaying the clock according to a received power supply; a power regulator, for generating the power supply to the DLL delay line according to a bias; a control logic, coupled to the clock receiver, for generating a plurality of logic signals respectively corresponding to a plurality of frequency ranges of the clock; and a bias generator, coupled between the control logic and the power regulator, for providing the bias to the power regulator, wherein the value of the bias is according to a logic signal output by the control logic.

Abstract: A DLL system that automatically resets after a frequency change of an external clock according to a phase difference includes: a clock receiver for receiving the external clock and generating a clock signal; a delay line, coupled to the clock receiver, for generating a delayed clock signal; a control loop, for tracking a phase difference between the clock signal and the delayed clock signal and locking the delay line when the phase difference is zero; and an N degrees phase detector (PD), coupled to the control loop, for detecting the phase difference between the clock signal and the delayed clock signal and outputting a positive signal when the detected phase difference is greater than N degrees, wherein the positive signal generates a reset signal to the DLL system.

Abstract: Disclosed herein are a method and structure, in an integrated circuit having at least one delay locked loop circuit (DLL), for determining a Lock Latency value of a DLL output clock signal. The disclosed method includes temporarily disabling a first clock signal in response to the DLL doing at least one of approaching and acquiring lock; and then thereafter determining a Lock Latency value in response to examining a DLL output clock signal generated in response to the first clock signal.

Abstract: Disclosed herein are a method and structure, in an integrated circuit having at least one delay locked loop circuit (DLL), for determining a Lock Latency value of a DLL output clock signal. The disclosed method includes temporarily disabling a first clock signal in response to the DLL doing at least one of approaching and acquiring lock; and then thereafter determining a Lock Latency value in response to examining a DLL output clock signal generated in response to the first clock signal.

Abstract: A method and structure to provide a circuit adapted to sense the status of a fuse includes an imbalanced sense amplifier latch which includes first and second nodes connected to the fuse. The first node is connected to a fuse and is weaker than the second node, allowing the first node to sense a different voltage level. The voltage difference between the nodes indicates the conductive status of the fuse.