Patents by Inventor John T. Stonick
John T. Stonick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973508Abstract: A system and method that measures the code non-linearity of a phase mixer (PMIX) during active operation of a clock and data recovery (CDR) circuitry. The PMIX circuitry generates a clock signal based on the PMIX codes. The PMIX circuitry receives a plurality of codes and based on the code value, adjusts the phase of the PMIX output clock signal. A number of times each of the plurality of PMIX codes occurs within a respective time period is determined. Non-linearity values are determined based on the number of times. The non-linearity values are stored in a memory.Type: GrantFiled: June 28, 2022Date of Patent: April 30, 2024Assignee: Synopsys, Inc.Inventors: Ayal S. Shoval, John T. Stonick, Michael W. Lynch, Dino Anthony Toffolon
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Patent number: 11962676Abstract: A system and method which compensates for phase mixer circuit non-linearities within a clock and data recovery (CDR) system during active operation. The CDR system includes compensation circuitry and phase accumulation circuitry. The compensation circuitry generates a first compensation signal based on a first compensation value. The phase accumulation circuitry receives the first compensation signal and a phase accumulator input update signal. The phase accumulation circuitry combines the first compensation signal with the phase accumulator input update signal to compensate for a first non-linearity within phase mixer (PMI) circuitry.Type: GrantFiled: June 28, 2022Date of Patent: April 16, 2024Assignee: Synopsys, Inc.Inventors: Ayal S. Shoval, Tom Thomas, Jin Chen, John T. Stonick, Michael W. Lynch, Dino Anthony Toffolon
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Publication number: 20230421159Abstract: A system and method that measures the code non-linearity of a phase mixer (PMIX) during active operation of a clock and data recovery (CDR) circuitry. The PMIX circuitry generates a clock signal based on the PMIX codes. The PMIX circuitry receives a plurality of codes and based on the code value, adjusts the phase of the PMIX output clock signal. A number of times each of the plurality of PMIX codes occurs within a respective time period is determined. Non-linearity values are determined based on the number of times. The non-linearity values are stored in a memory.Type: ApplicationFiled: June 28, 2022Publication date: December 28, 2023Inventors: Ayal S. SHOVAL, John T. STONICK, Michael W. LYNCH, Dino Anthony TOFFOLON
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Publication number: 20230421344Abstract: A system and method which compensates for phase mixer circuit non-linearities within a clock and data recovery (CDR) system during active operation. The CDR system includes compensation circuitry and phase accumulation circuitry. The compensation circuitry generates a first compensation signal based on a first compensation value. The phase accumulation circuitry receives the first compensation signal and a phase accumulator input update signal. The phase accumulation circuitry combines the first compensation signal with the phase accumulator input update signal to compensate for a first non-linearity within phase mixer (PMI) circuitry.Type: ApplicationFiled: June 28, 2022Publication date: December 28, 2023Inventors: Ayal S. SHOVAL, Tom THOMAS, Jin CHEN, John T. STONICK, Michael W. LYNCH, Dino Anthony TOFFOLON
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Publication number: 20230141608Abstract: A re-timer device includes transceiver circuitry. The transceiver circuitry includes clock generation circuitry and first receiver circuitry. The clock generation circuitry generates a first clock signal. The first receiver circuitry receives the first clock signal and a first input signal. The first receiver circuitry generates a first frequency offset value based on the first input signal and the first clock signal. The first input signal has a first frequency and the first clock signal has a second frequency different than the first frequency. The first receiver circuitry outputs the first frequency offset value.Type: ApplicationFiled: November 4, 2022Publication date: May 11, 2023Inventors: Gopal Krishna Ullal NAYAK, Sanket Sanjay NAIK, Ankit SOMANI, Biman CHATTOPADHYAY, Ravi Jitendra MEHTA, Sujoy CHAKRAVARTY, Ameer Muhammad YOUSSEF, Ayal S. SHOVAL, John T. STONICK, Michael W. LYNCH, Adam Ross BURNS
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Patent number: 10944406Abstract: A CDR method/circuit utilizes a closed-loop clock alignment circuit and a duplicate clock to align a sampling point clock to both mid-interval and optimal sample point phases during data receiving processes. An initial clock is generated having the mid-interval sampling point phase, then the closed-loop clock alignment circuit generates a phase correction signal based on a phase difference between the data sampling clock and the initial clock, and then the phase correction signal is fed back to a high-speed phase mixer to adjust/align the sampling point clock to the initial clock. Subsequently, the duplicate clock is generated and utilized to determine an optimal sampling point phase while the data sampling clock is utilized to read the received data signal, and then the closed-loop clock alignment circuit is re-used to re-align the data sampling clock to the duplicate clock when the optimal sampling point phase is identified.Type: GrantFiled: October 16, 2019Date of Patent: March 9, 2021Assignee: Synopsys, Inc.Inventors: Zhenchang Du, Choon H. Leong, David A. Yokoyama-Martin, John T. Stonick, Skye Wolfer
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Patent number: 9049020Abstract: Circuitry to facilitate testing of serial interfaces is described. Specifically, some embodiments of the present invention facilitate testing the clock and data recovery functionality of a receiver. A serial interface can include a multiplying phase locked loop (MPLL) clock generator, a transmitter, and a receiver. The MPLL clock generator can generate a first clock signal and a second clock signal, and can vary a phase and/or frequency difference between the first clock signal and the second clock signal. During test, the transmitter and the receiver can be directly or capacitively coupled to each another. Specifically, during test, the serial interface can be configured so that the transmitter transmits data using the first clock signal, and the receiver receives data using the second clock signal. The clock and data recovery functionality of the receiver can be tested by comparing the transmitted data with the received data.Type: GrantFiled: June 2, 2010Date of Patent: June 2, 2015Assignee: SYNOPSYS, INC.Inventors: James P. Flynn, Junqi Hua, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
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Patent number: 8589708Abstract: Some embodiments provide a clock and data recovery (CDR) system to recover clock and data information from an analog signal. The CDR system may include an integral path and a proportional path that are part of an integral-proportional control loop. The integral path may be used to track frequency changes in a clock signal that is embedded in the analog signal, while the proportional path may be used to track phase changes in the clock signal that is embedded in the analog signal. The proportional path may be executed at a first clock frequency, while the integral path may be executed at a second clock frequency that is lower than the first clock frequency to reduce the power consumption of the CDR system.Type: GrantFiled: June 9, 2010Date of Patent: November 19, 2013Assignee: Synopsys, Inc.Inventors: James P. Flynn, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
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Patent number: 8526551Abstract: An integrated circuit that includes a receive data path is described. The receive data path: equalizes a received analog signal, converts the resulting equalized analog signal to digital data values based on a clock signal, and recovers the clock signal in the digital data values. The integrated circuit also includes an on-chip oscilloscope. The oscilloscope includes: two comparators, a phase rotator that outputs an oscilloscope clock signal whose phase can be varied relative to that of the recovered clock signal, and an offset circuit that outputs a voltage offset. Based on the voltage offset and the oscilloscope clock signal, the comparators output digital values which can be used to determine eye patterns that correspond to the analog signal before and after equalization. The eye patterns can then be correlated with an error rate associated with the received data.Type: GrantFiled: June 1, 2010Date of Patent: September 3, 2013Assignee: Synopsys, Inc.Inventors: James P. Flynn, Junqi Hua, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
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Patent number: 8477898Abstract: One embodiment of the present invention provides a phase-locked loop (PLL) for synthesizing a fractional frequency. The PLL can include a 1/N frequency divider, a voltage-controlled oscillator (VCO), a programmable phase mixer, and a phase detector. The programmable phase mixer can be coupled between an output of the VCO and an input of the frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock signal of frequency f1 by varying a phase of the output clock signal. The frequency divider is configured to receive the first clock signal from the programmable phase mixer and generate a second clock signal of frequency f2=f1/N. The phase detector can receive a reference clock signal and the second clock signal as inputs, and the phase detector's output can be used to generate the control voltage for the VCO.Type: GrantFiled: June 21, 2010Date of Patent: July 2, 2013Assignee: Synopsys, Inc.Inventors: James P. Flynn, Richard H. Steeves, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin, Dino A. Toffolon, Jasjeet Singh
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Patent number: 8208591Abstract: Systems and techniques for adapting and/or optimizing an equalizer of a receiver are described. The equalizer's behavior can be adjusted by modifying one or more equalization parameters. At the beginning of the adaptation and/or optimization process, the system can determine robust initial values for the one or more equalization parameters. The system can then adapt and/or optimize the equalizer by iteratively adjusting the one or more equalization parameters. Specifically, in each iteration, the system can use the receiver's clock and data recovery (CDR) circuitry to determine the number of early and late data transitions associated with one or more data patterns. Next, the system can adjust the one or more equalization parameters so that, for each data pattern in the one or more data patterns, the ratio between the number of early data transitions and the number of late data transitions is substantially equal to a desired value.Type: GrantFiled: June 21, 2010Date of Patent: June 26, 2012Assignee: Synopsys, Inc.Inventors: James P. Flynn, Junqi Hua, Robert B. Lefferts, Richard H. Steeves, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
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Patent number: 8184757Abstract: An on-die scope is described. The on-die scope can include one or more scope slicers, phase sweeping circuitry, voltage sweeping circuitry, and eye-diagram data collection circuitry. The clock and data recovery circuitry can receive an input signal, and output a recovered clock signal and a recovered bit-stream. The phase sweeping circuitry can receive the recovered clock signal, and output the scope clock signal by adding a phase offset to the recovered clock signal. A scope slicer can receive the voltage threshold, the scope clock signal, and the input signal, and output a scope bit-stream. The eye-diagram data collection circuitry can detect one or more bit-patterns in the recovered bit-stream, and modify values of one or more scope counters based solely or partly on the scope bit-stream and the recovered bit-stream.Type: GrantFiled: June 21, 2010Date of Patent: May 22, 2012Assignee: Synopsys, Inc.Inventors: James P. Flynn, Junqi Hua, Robert B. Lefferts, Richard H. Steeves, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
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Patent number: 8125245Abstract: Some embodiments of the present invention provide a voltage-mode transmitter. The transmitter can include configuration circuitry, bias circuitry, and a set of driver slices. Each driver slice can include driver transistors which drive an output value. The outputs of each driver slice can be directly or capacitively coupled with the transmitter's outputs. Each driver slice can also include one or more impedance-matching transistors which are serially coupled to at least some of the driver transistors. The configuration circuitry can configure a subset of driver slices so that the down (or up) impedance of the transmitter is within a first tolerance of a desired impedance value. The bias circuitry can bias the one or more impedance-matching transistors in each driver slice in the subset of driver slices so that the up (or down) impedance is within a second tolerance of the down (or up) impedance.Type: GrantFiled: June 21, 2010Date of Patent: February 28, 2012Assignee: Synopsys, Inc.Inventors: James P. Flynn, Junqi Hua, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
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Publication number: 20110310947Abstract: Systems and techniques for adapting and/or optimizing an equalizer of a receiver are described. The equalizer's behavior can be adjusted by modifying one or more equalization parameters. At the beginning of the adaptation and/or optimization process, the system can determine robust initial values for the one or more equalization parameters. The system can then adapt and/or optimize the equalizer by iteratively adjusting the one or more equalization parameters. Specifically, in each iteration, the system can use the receiver's clock and data recovery (CDR) circuitry to determine the number of early and late data transitions associated with one or more data patterns. Next, the system can adjust the one or more equalization parameters so that, for each data pattern in the one or more data patterns, the ratio between the number of early data transitions and the number of late data transitions is substantially equal to a desired value.Type: ApplicationFiled: June 21, 2010Publication date: December 22, 2011Applicant: SYNOPSYS, INC.Inventors: James P. Flynn, Junqi Hua, Robert B. Lefferts, Richard H. Steeves, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
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Publication number: 20110310942Abstract: One embodiment of the present invention provides a phase-locked loop (PLL) for synthesizing a fractional frequency. The PLL can include a 1/N frequency divider, a voltage-controlled oscillator (VCO), a programmable phase mixer, and a phase detector. The programmable phase mixer can be coupled between an output of the VCO and an input of the frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock signal of frequency f1 by varying a phase of the output clock signal. The frequency divider is configured to receive the first clock signal from the programmable phase mixer and generate a second clock signal of frequency f2=f1/N. The phase detector can receive a reference clock signal and the second clock signal as inputs, and the phase detector's output can be used to generate the control voltage for the VCO.Type: ApplicationFiled: June 21, 2010Publication date: December 22, 2011Applicant: SYNOPSYS, INC.Inventors: James P. Flynn, Richard H. Steeves, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin, Dino A. Toffolon, Jasjeet Singh
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Publication number: 20110311009Abstract: An on-die scope is described. The on-die scope can include one or more scope slicers, phase sweeping circuitry, voltage sweeping circuitry, and eye-diagram data collection circuitry. The clock and data recovery circuitry can receive an input signal, and output a recovered clock signal and a recovered bit-stream. The phase sweeping circuitry can receive the recovered clock signal, and output the scope clock signal by adding a phase offset to the recovered clock signal. A scope slicer can receive the voltage threshold, the scope clock signal, and the input signal, and output a scope bit-stream. The eye-diagram data collection circuitry can detect one or more bit-patterns in the recovered bit-stream, and modify values of one or more scope counters based solely or partly on the scope bit-stream and the recovered bit-stream.Type: ApplicationFiled: June 21, 2010Publication date: December 22, 2011Applicant: SYNOPSYS, INC.Inventors: James P. Flynn, Junqi Hua, Robert B. Lefferts, Richard H. Steeves, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
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Publication number: 20110309857Abstract: Some embodiments of the present invention provide a voltage-mode transmitter. The transmitter can include configuration circuitry, bias circuitry, and a set of driver slices. Each driver slice can include driver transistors which drive an output value. The outputs of each driver slice can be directly or capacitively coupled with the transmitter's outputs. Each driver slice can also include one or more impedance-matching transistors which are serially coupled to at least some of the driver transistors. The configuration circuitry can configure a subset of driver slices so that the down (or up) impedance of the transmitter is within a first tolerance of a desired impedance value. The bias circuitry can bias the one or more impedance-matching transistors in each driver slice in the subset of driver slices so that the up (or down) impedance is within a second tolerance of the down (or up) impedance.Type: ApplicationFiled: June 21, 2010Publication date: December 22, 2011Applicant: SYNOPSYS, INC.Inventors: James P. Flynn, Junqi Hua, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
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Publication number: 20110307722Abstract: Some embodiments provide a clock and data recovery (CDR) system to recover clock and data information from an analog signal. The CDR system may include an integral path and a proportional path that are part of an integral-proportional control loop. The integral path may be used to track frequency changes in a clock signal that is embedded in the analog signal, while the proportional path may be used to track phase changes in the clock signal that is embedded in the analog signal. The proportional path may be executed at a first clock frequency, while the integral path may be executed at a second clock frequency that is lower than the first clock frequency to reduce the power consumption of the CDR system.Type: ApplicationFiled: June 9, 2010Publication date: December 15, 2011Applicant: SYNOPSYS, INC.Inventors: James P. Flynn, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
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Publication number: 20110302452Abstract: Circuitry to facilitate testing of serial interfaces is described. Specifically, some embodiments of the present invention facilitate testing the clock and data recovery functionality of a receiver. A serial interface can include a multiplying phase locked loop (MPLL) clock generator, a transmitter, and a receiver. The MPLL clock generator can generate a first clock signal and a second clock signal, and can vary a phase and/or frequency difference between the first clock signal and the second clock signal. During test, the transmitter and the receiver can be directly or capacitively coupled to each another. Specifically, during test, the serial interface can be configured so that the transmitter transmits data using the first clock signal, and the receiver receives data using the second clock signal. The clock and data recovery functionality of the receiver can be tested by comparing the transmitted data with the received data.Type: ApplicationFiled: June 2, 2010Publication date: December 8, 2011Applicant: SYNOPSYS, INC.Inventors: James P. Flynn, Junqi Hua, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
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Publication number: 20110292990Abstract: An integrated circuit that includes a receive data path is described. The receive data path: equalizes a received analog signal, converts the resulting equalized analog signal to digital data values based on a clock signal, and recovers the clock signal in the digital data values. The integrated circuit also includes an on-chip oscilloscope. The oscilloscope includes: two comparators, a phase rotator that outputs an oscilloscope clock signal whose phase can be varied relative to that of the recovered clock signal, and an offset circuit that outputs a voltage offset. Based on the voltage offset and the oscilloscope clock signal, the comparators output digital values which can be used to determine eye patterns that correspond to the analog signal before and after equalization. The eye patterns can then be correlated with an error rate associated with the received data.Type: ApplicationFiled: June 1, 2010Publication date: December 1, 2011Applicant: SYNOPSYS, INC.Inventors: James P. Flynn, Junqi Hua, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin