Abstract: An image sensor testing apparatus is disclosed. The image sensor testing apparatus includes an electronic test system having a light source for illuminating an image sensor wafer to generate pixel data and a host processor for receiving the pixel data. An interface card coupled to the electronic test system has a programmable processor for processing the pixel data to generate processed data, the processed data transmitted to and analyzed by the host processor together with the pixel data to detect pixel defects in the image sensor wafer.

Abstract: An image sensor testing apparatus is disclosed. The image sensor testing apparatus includes an electronic test system having a light source for illuminating an image sensor wafer to generate pixel data and a host processor for receiving the pixel data. An interface card coupled to the electronic test system has a programmable processor for processing the pixel data to generate processed data, the processed data transmitted to and analyzed by the host processor together with the pixel data to detect pixel defects in the image sensor wafer.

Abstract: A field effect transistor is formed across a one or more trenches (26) or bars (120), thereby increasing the effective width of the channel region and the current-carrying capacity of the device.

Abstract: A field effect transistor is formed across one or more trenches (26) or bars (120), thereby increasing the effective width of the channel region and the current-carrying capacity of the device.

Abstract: Floating gates of nonvolatile memory cells are formed in pairs within a pyramidal or truncated pyramidal opening in a semiconductor layer between a top surface thereof and a heavily doped source region spaced from the surface of the semiconductor layer. The floating gates control the conductance of channel regions formed along the sloped sidewalls of the pyramidal openings between surface drains and the buried source region.

Abstract: A substantially constant current is conducted in a first direction through an interconnect structure having a barrier layer to determine the lifetime of the structure in the first current direction. A substantially identical current is conducted in a second direction through a substantially identical interconnect structure to determine the lifetime of the structure in the second current direction. These tests are repeated for identical structures but having different barrier layer thicknesses. The results of these lifetime tests are compared to determine the barrier layer's effect on electromigration in the structure, which can be used to design the barrier layer to optimize the structure's lifetime and speed.

Abstract: A substantially constant current is conducted in a first direction through an interconnect structure having a barrier layer to determine the lifetime of the structure in the first current direction. A substantially identical current is conducted in a second direction through a substantially identical interconnect structure to determine the lifetime of the structure in the second current direction. These tests are repeated for identical structures but having different barrier layer thicknesses. The results of these lifetime tests are compared to determine the barrier layer's effect on electromigration in the structure, which can be used to design the barrier layer to optimize the structure's lifetime and speed.

Abstract: A test method and apparatus are provided for predicting hot-carrier induced leakage over time in IGFET's. Test results are used to show how choice of channel length and stress voltages critically affect hot-carrier-induced leakage (HCIL) leakage over time, particularly in devices having submicron channel lengths. Models are developed for predicting leakage current over the long term given short term test results. Alternative design strategies are proposed for reliably satisfying long term leakage requirements.

Abstract: A test method and apparatus are provided for predicting hot-carrier induced leakage over time in IGFET's. Test results are used to show how choice of channel length and stress voltages critically affect hot-carrier-induced leakage (HCIL) leakage over time, particularly in devices having submicron channel lengths. Models are developed for predicting leakage current over the long term given short term test results. Alternative design strategies are proposed for reliably satisfying long term leakage requirements.

Abstract: Voids in a metallization pattern comprising a barrier layer, such as those generated by stress migration, are detected by applying a current across a test section of the metallization pattern to generate hot spots which are detected as by employing an infrared microscope or with a liquid crystalline material.