Abstract: A packet switching node in a pipelined architecture processing packets received via an input port associated with the packet switching node performs a method, which includes: determining a packet frame type; selectively extracting packet header field values specific to a packet frame type, including packet addressing information; ascribing to the packet a preliminary action to be performed; searching packet switching information tracked by the packet switching node based on extracted packet addressing information; formulating a preliminary switch response for the packet; classifying the packet into a packet flow; modifying the preliminary switch response in accordance with one of the preliminary action, the packet flow into which the packet was classified, and a default port action corresponding to the input port; modifying the packet header in accordance with one of the preliminary action, the packet flow, and the default port action; and processing the packet.

Abstract: A packet switching node having a pipelined packet processing architecture processing packets received via an input port associated with the packet switching node is presented.

Abstract: A method of forwarding messages among task blocks using a task manager. The task manager receiving the message at an input port. The method further comprises determining the destination of the message. The message is stored in a pre-allocated segment that is selected from a plurality of segments within an input buffer. Each pre-allocated segment is associated with an output buffer. The method further comprising moving the message to the output buffer associated with the pre-allocated segment by an arbitrator that uses a round robin scheme for polling each input port. The pre-allocated segment is selected based on the destination of the message. The message may further comprise a priority, wherein the message is routed to a switch plane based on the message control signals. The higher priority switch plane given priority whenever there is a resource conflict.

Abstract: A high speed data communication controller comprising two independent central processing units, each having its own independent program instruction fetch data path, and instruction execution data path. The data communication controller includes a dual-port serial communication subsystem and a bus interface unit operably associated with a four channel DMA controller. One central processing unit is assigned the task of handling the medium access control (MAC) layer function of a multilayered local area network protocol, while the other central processing unit handles host commands and buffer memory management functions associated with the transmission and reception of packets relating to the higher layer protocol. As a result of the present invention, efficient data communication processing is achieved within a single VSLI chip, thereby improving node and network data throughout.