Patents by Inventor John T. Chen

John T. Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7970600
    Abstract: A computer-implemented method for developing a parser is provided. The method includes accessing a corpus of sentences and parsing the sentences to generate a structural description of each sentence. The parser is trained based on the structural description of each sentence.
    Type: Grant
    Filed: November 3, 2004
    Date of Patent: June 28, 2011
    Assignee: Microsoft Corporation
    Inventors: John T. Chen, Ming Zhou, Tianlei Wu
  • Patent number: 7128631
    Abstract: A system and method are described for self-aligning electrodes for color filters of passive matrix displays.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: October 31, 2006
    Assignee: Surface Logix, Inc.
    Inventors: Christopher H. McCoy, John T. Chen, David R. Beaulieu
  • Publication number: 20040266307
    Abstract: A system and method are described for self-aligning electrodes for color filters of passive matrix displays.
    Type: Application
    Filed: November 14, 2003
    Publication date: December 30, 2004
    Applicant: Surface Logix, Inc.
    Inventors: Christopher H. McCoy, John T. Chen, David R. Beaulieu
  • Publication number: 20040261981
    Abstract: A thermal management material that may be used is thermal interface material is described. An apparatus and methods of the making the thermal management material are also described, which includes a roll-to-roll apparatus for making the thermal management material.
    Type: Application
    Filed: November 13, 2003
    Publication date: December 30, 2004
    Applicant: Surface Logix, Inc.
    Inventors: Christopher H. McCoy, John T. Chen, David R. Beaulieu
  • Patent number: 6421794
    Abstract: A method and apparatus for diagnosing memory using self—testing circuits. A comparator compares actual data output from a RAM with expected output generated by built—in self—testing (BIST) circuitry. The comparator outputs a resulting initial fail vector which is subsequently input into a compressor. The compressor performs multiple logical operations on the initial fail vector to compress or reduce the bit—width of the initial fail vector, resulting in a compressed fail vector. Once generated, the compressed fail vector is fed to I/O terminals of the integrated circuit (IC) forming a stream of bits to be recorded by test equipment external to the IC. The recorded compressed fail vector is then utilized to reconstruct the initial fail vector that was generated by the bit comparator.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: July 16, 2002
    Inventors: John T. Chen, Janusz Rajski