Patents by Inventor John Te-Jui Sheu

John Te-Jui Sheu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210081815
    Abstract: The disclosure derives insight from telemetry data by receiving telemetry data; parsing the received telemetry data to identify properties, and mapping the identified properties to a set of identified tags based at least on a tag library. Based at least on the mapping, the disclosure generates insight data and a report for the telemetry data. In this manner, the disclosure adds structure to data, thereby providing semantic meaning to internet of things (IoT) telemetry data, regardless of the device class or manufacturer. This, in turn, automatically creates applicable insights. Insights are available with a core tag taxonomy, which can be extended and customized. By applying the tags, a user obtains immediate insights related to usage, performance, and health of a monitored product or service.
    Type: Application
    Filed: November 18, 2019
    Publication date: March 18, 2021
    Inventors: Shloma BAUM, Jimmy Chih-Hsun YU, John Te-Jui SHEU
  • Publication number: 20180321966
    Abstract: Various aspects are disclosed herein for attenuating spin waiting in a virtual machine environment comprising a plurality of virtual machines and virtual processors. Selected virtual processors can be given time slice extensions in order to prevent such virtual processors from becoming de-scheduled (and hence causing other virtual processors to have to spin wait). Selected virtual processors can also be expressly scheduled so that they can be given higher priority to resources, resulting in reduced spin waits for other virtual processors waiting on such selected virtual processors. Finally, various spin wait detection techniques can be incorporated into the time slice extension and express scheduling mechanisms, in order to identify potential and existing spin waiting scenarios.
    Type: Application
    Filed: July 10, 2018
    Publication date: November 8, 2018
    Inventors: Yau Ning Chin, John Te-Jui Sheu, Arun Kishan, Thomas Fahrig, Rene Antonio Vega
  • Patent number: 10067782
    Abstract: Various aspects are disclosed herein for attenuating spin waiting in a virtual machine environment comprising a plurality of virtual machines and virtual processors. Selected virtual processors can be given time slice extensions in order to prevent such virtual processors from becoming de-scheduled (and hence causing other virtual processors to have to spin wait). Selected virtual processors can also be expressly scheduled so that they can be given higher priority to resources, resulting in reduced spin waits for other virtual processors waiting on such selected virtual processors. Finally, various spin wait detection techniques can be incorporated into the time slice extension and express scheduling mechanisms, in order to identify potential and existing spin waiting scenarios.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: September 4, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yau Ning Chin, John Te-Jui Sheu, Arun Kishan, Thomas Fahrig, Rene Antonio Vega
  • Publication number: 20160154666
    Abstract: Various aspects are disclosed herein for attenuating spin waiting in a virtual machine environment comprising a plurality of virtual machines and virtual processors. Selected virtual processors can be given time slice extensions in order to prevent such virtual processors from becoming de-scheduled (and hence causing other virtual processors to have to spin wait). Selected virtual processors can also be expressly scheduled so that they can be given higher priority to resources, resulting in reduced spin waits for other virtual processors waiting on such selected virtual processors. Finally, various spin wait detection techniques can be incorporated into the time slice extension and express scheduling mechanisms, in order to identify potential and existing spin waiting scenarios.
    Type: Application
    Filed: November 18, 2015
    Publication date: June 2, 2016
    Inventors: Yau Ning Chin, John Te-Jui Sheu, Arun Kishan, Thomas Fahrig
  • Patent number: 9201673
    Abstract: Various aspects are disclosed herein for attenuating spin waiting in a virtual machine environment comprising a plurality of virtual machines and virtual processors. Selected virtual processors can be given time slice extensions in order to prevent such virtual processors from becoming de-scheduled (and hence causing other virtual processors to have to spin wait). Selected virtual processors can also be expressly scheduled so that they can be given higher priority to resources, resulting in reduced spin waits for other virtual processors waiting on such selected virtual processors. Finally, various spin wait detection techniques can be incorporated into the time slice extension and express scheduling mechanisms, in order to identify potential and existing spin waiting scenarios.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: December 1, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yau Ning Chin, Rene Antonio Vega, John Te-Jui Sheu, Arun Kishan, Thomas Fahrig
  • Patent number: 9104594
    Abstract: Various mechanisms are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, one mechanism fills in entries in a shadow page table (SPT) and additionally, speculatively fills in other entries in the SPT based on various heuristics. Another mechanism allows virtual TLBs (translation look-aside buffers) to cache partial walks in a guest page table tree. Still another mechanism allows for dynamic resizing of the virtual TLB to optimize for run-time characteristics of active workloads. Still another mechanism allows virtual machine monitors (VMMs) to support legacy and enlightened modes of virtual TLB operation. Finally, another mechanism allows the VMM to remove only the stale entries in SPTs when linking or switching address spaces. All these mechanisms, together or in part, increase the operational efficiency of the virtual TLB.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: August 11, 2015
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Ernest S. Cohen, John Te-Jui Sheu, Landy Wang, Matthew D. Hendel, Rene Antonio Vega, Sharvil A. Nanavati
  • Publication number: 20140122830
    Abstract: Various mechanisms are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, one mechanism fills in entries in a shadow page table (SPT) and additionally, speculatively fills in other entries in the SPT based on various heuristics. Another mechanism allows virtual TLBs (translation look-aside buffers) to cache partial walks in a guest page table tree. Still another mechanism allows for dynamic resizing of the virtual TLB to optimize for run-time characteristics of active workloads. Still another mechanism allows virtual machine monitors (VMMs) to support legacy and enlightened modes of virtual TLB operation. Finally, another mechanism allows the VMM to remove only the stale entries in SPTs when linking or switching address spaces. All these mechanisms, together or in part, increase the operational efficiency of the virtual TLB.
    Type: Application
    Filed: December 23, 2013
    Publication date: May 1, 2014
    Applicant: Microsoft Corporation
    Inventors: Ernest S. Cohen, John Te-Jui Sheu, Landy Wang, Matthew D. Hendel, Rene Antonio Vega, Sharvil A. Nanavati
  • Patent number: 8694712
    Abstract: Various operations are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, operations are disclosed that allow for determination of whether present entries in shadow page tables (SPTs) are stale by comparing shadowed guest page table (GPT) entries against snapshots taken when the entries were cached. Other operations are disclosed that allow a virtual machine monitor (VMM) to access shadow page table trees (SPTTs) by walking trees in software or in hardware. Still other operations are disclosed allowing the VMM to use a hash table to relate GVA ranges to SPTs that map them, thus significantly reducing the cost of having to walk each SPTT in order to invalidate desired GVA(s). And, finally, operations are disclosed allowing the VMM to determine global GVA ranges by checking a bitmap, when invalidating global GVAs.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: April 8, 2014
    Assignee: Microsoft Corporation
    Inventors: John Te-Jui Sheu, Matthew D. Hendel, Landy Wang, Ernest S. Cohen, Rene Antonio Vega, Sharvil A. Nanavati
  • Patent number: 8615643
    Abstract: Various mechanisms are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, one mechanism fills in entries in a shadow page table (SPT) and additionally, speculatively fills in other entries in the SPT based on various heuristics. Another mechanism allows virtual TLBs (translation look-aside buffers) to cache partial walks in a guest page table tree. Still another mechanism allows for dynamic resizing of the virtual TLB to optimize for run-time characteristics of active workloads. Still another mechanism allows virtual machine monitors (VMMs) to support legacy and enlightened modes of virtual TLB operation. Finally, another mechanism allows the VMM to remove only the stale entries in SPTs when linking or switching address spaces. All these mechanisms, together or in part, increase the operational efficiency of the virtual TLB.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: December 24, 2013
    Assignee: Microsoft Corporation
    Inventors: Ernest S. Cohen, John Te-Jui Sheu, Landy Wang, Matthew D. Hendel, Rene Antonio Vega, Sharvil A. Nanavati
  • Patent number: 8095771
    Abstract: A method of virtualizing memory through shadow page tables that cache translations from multiple guest address spaces in a virtual machine includes a software version of a hardware tagged translation look-aside buffer. Edits to guest page tables are detected by intercepting the creation of guest-writable mappings to guest page tables with translations cached in shadow page tables. The affected cached translations are marked as stale and purged upon an address space switch or an indiscriminate flush of translations by the guest. Thereby, non-stale translations remain cached but stale translations are discarded. The method includes tracking the guest-writable mappings to guest page tables, deferring discovery of such mappings to a guest page table for the first time until a purge of all cached translations when the number of untracked guest page tables exceeds a threshold, and sharing shadow page tables between shadow address spaces and between virtual processors.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: January 10, 2012
    Assignee: Microsoft Corporation
    Inventors: John Te-Jui Sheu, David S. Bailey, Eric P. Traut, Renee Antonio Vega
  • Patent number: 7913009
    Abstract: Example operations related to deferring interrupts are herein disclosed. In one example embodiment, a method includes, but is not limited to, writing a message to a memory location shared between a sender and a receiver; and requesting that an interrupt be transmitted to the receiver after a specified latency has elapsed, wherein an interrupt that is pending is stored in a trigger memory. It can be appreciated by one of skill in the art that one or more various aspects of the disclosure may include but are not limited to circuitry and/or programming for effecting the herein-referenced aspects; the circuitry and/or programming can be virtually any combination of hardware, software, and/or firmware configured to effect the herein-referenced aspects depending upon the design choices of the system designer. In addition to the foregoing, other aspects are described in the claims, drawings, and text forming a part of the present application.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: March 22, 2011
    Assignee: Microsoft Corporation
    Inventors: René Vega, John Te-Jui Sheu, Yau Ning Chin
  • Patent number: 7788464
    Abstract: Various operations are provided that improve the scalability of virtual TLBs in multi-processor virtual machines, and they include: implicitly locking SPTs using per-processor generation counters; waiting for pending fills on other virtual processors to complete before servicing a GVA invalidation using the counters; write-protecting or unmaping guest pages in a deferred two-stage process or reclaiming SPTs in a deferred two-stage process; periodically coalescing two SPTs that shadow the same GPT with the same attributes; sharing SPTs between two SASes only at a specified level in a SPTT; flushing the entire virtual TLB using a generation counter; allocating a SPT to GPT from a NUMA node on which the GPT resides; having an instance for each NUMA node on which a virtual machine runs; and, correctly handling the serializing instructions executed by a guest in a virtual machine with more than one virtual processor sharing the virtual TLB.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: August 31, 2010
    Assignee: Microsoft Corporation
    Inventors: John Te-Jui Sheu, Ernest S. Cohen, Matthew D. Hendel, Landy Wang, Rene Antonio Vega, Sharvil A. Nanavati
  • Publication number: 20100031254
    Abstract: Various aspects are disclosed herein for attenuating spin waiting in a virtual machine environment comprising a plurality of virtual machines and virtual processors. Selected virtual processors can be given time slice extensions in order to prevent such virtual processors from becoming de-scheduled (and hence causing other virtual processors to have to spin wait). Selected virtual processors can also be expressly scheduled so that they can be given higher priority to resources, resulting in reduced spin waits for other virtual processors waiting on such selected virtual processors. Finally, various spin wait detection techniques can be incorporated into the time slice extension and express scheduling mechanisms, in order to identify potential and existing spin waiting scenarios.
    Type: Application
    Filed: July 30, 2008
    Publication date: February 4, 2010
    Applicant: Microsoft Corporation
    Inventors: Yau Ning Chin, Rene Antonio Vega, John Te-Jui Sheu, Arun Kishan, Thomas Fahrig
  • Publication number: 20080320194
    Abstract: Example operations related to deferring interrupts are herein disclosed. In one example embodiment, a method includes, but is not limited to, writing a message to a memory location shared between a sender and a receiver; and requesting that an interrupt be transmitted to the receiver after a specified latency has elapsed, wherein an interrupt that is pending is stored in a trigger memory. It can be appreciated by one of skill in the art that one or more various aspects of the disclosure may include but are not limited to circuitry and/or programming for effecting the herein-referenced aspects; the circuitry and/or programming can be virtually any combination of hardware, software, and/or firmware configured to effect the herein-referenced aspects depending upon the design choices of the system designer. In addition to the foregoing, other aspects are described in the claims, drawings, and text forming a part of the present application.
    Type: Application
    Filed: June 20, 2007
    Publication date: December 25, 2008
    Applicant: Microsoft Corporation
    Inventors: Rene Vega, John Te-Jui Sheu, Yau Ning Chin
  • Patent number: 7434003
    Abstract: An operating system is described that is capable of ascertaining whether it is executing in a virtual machine environment and is further capable of modifying its behavior to operate more efficiently and provide optimal behavior in a virtual machine environment. An operating system is enlightened so that it is aware of VMMs or hypervisors, taking on behavior that is optimal to that environment. The VMM or hypervisor informs the operating system of the optimal behavior, and vice versa.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: October 7, 2008
    Assignee: Microsoft Corporation
    Inventors: Adrian J. Oney, Bryan Mark Willman, Eric P. Traut, Forrest Curtis Foltz, John Te-Jui Sheu, Matthew D. Hendel, Rene Antonio Vega
  • Publication number: 20080215848
    Abstract: A method of virtualizing memory through shadow page tables that cache translations from multiple guest address spaces in a virtual machine includes a software version of a hardware tagged translation look-aside buffer. Edits to guest page tables are detected by intercepting the creation of guest-writable mappings to guest page tables with translations cached in shadow page tables. The affected cached translations are marked as stale and purged upon an address space switch or an indiscriminate flush of translations by the guest. Thereby, non-stale translations remain cached but stale translations are discarded. The method includes tracking the guest-writable mappings to guest page tables, deferring discovery of such mappings to a guest page table for the first time until a purge of all cached translations when the number of untracked guest page tables exceeds a threshold, and sharing shadow page tables between shadow address spaces and between virtual processors.
    Type: Application
    Filed: April 7, 2008
    Publication date: September 4, 2008
    Inventors: John Te-Jui Sheu, David S. Bailey, Eric P. Traut, Rene Antonio Vega
  • Publication number: 20080155168
    Abstract: Various operations are provided that improve the scalability of virtual TLBs in multi-processor virtual machines, and they include: implicitly locking SPTs using per-processor generation counters; waiting for pending fills on other virtual processors to complete before servicing a GVA invalidation using the counters; write-protecting or unmaping guest pages in a deferred two-stage process or reclaiming SPTs in a deferred two-stage process; periodically coalescing two SPTs that shadow the same GPT with the same attributes; sharing SPTs between two SASes only at a specified level in a SPTT; flushing the entire virtual TLB using a generation counter; allocating a SPT to GPT from a NUMA node on which the GPT resides; having an instance for each NUMA node on which a virtual machine runs; and, correctly handling the serializing instructions executed by a guest in a virtual machine with more than one virtual processor sharing the virtual TLB.
    Type: Application
    Filed: December 22, 2006
    Publication date: June 26, 2008
    Applicant: Microsoft Corporation
    Inventors: John Te-Jui Sheu, Ernest S. Cohen, Matthew D. Hendel, Landy Wang, Rene Antonio Vega, Sharvil A. Nanavati
  • Publication number: 20080133875
    Abstract: Various mechanisms are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, one mechanism fills in entries in a shadow page table (SPT) and additionally, speculatively fills in other entries in the SPT based on various heuristics. Another mechanism allows virtual TLBs (translation look-aside buffers) to cache partial walks in a guest page table tree. Still another mechanism allows for dynamic resizing of the virtual TLB to optimize for run-time characteristics of active workloads. Still another mechanism allows virtual machine monitors (VMMs) to support legacy and enlightened modes of virtual TLB operation. Finally, another mechanism allows the VMM to remove only the stale entries in SPTs when linking or switching address spaces. All these mechanisms, together or in part, increase the operational efficiency of the virtual TLB.
    Type: Application
    Filed: December 5, 2006
    Publication date: June 5, 2008
    Applicant: Microsoft Corporation
    Inventors: Ernest S. Cohen, John Te-Jui Sheu, Landy Wang, Matthew D. Hendel, Rene Antonio Vega, Sharvil A. Nanavati
  • Publication number: 20080134174
    Abstract: Various operations are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, operations are disclosed that allow for determination of whether present entries in shadow page tables (SPTs) are stale by comparing shadowed guest page table (GPT) entries against snapshots taken when the entries were cached. Other operations are disclosed that allow a virtual machine monitor (VMM) to access shadow page table trees (SPTTs) by walking trees in software or in hardware. Still other operations are disclosed allowing the VMM to use a hash table to relate GVA ranges to SPTs that map them, thus significantly reducing the cost of having to walk each SPTT in order to invalidate desired GVA(s). And, finally, operations are disclosed allowing the VMM to determine global GVA ranges by checking a bitmap, when invalidating global GVAs.
    Type: Application
    Filed: December 5, 2006
    Publication date: June 5, 2008
    Applicant: Microsoft Corporation
    Inventors: John Te-Jui Sheu, Matthew D. Hendel, Landy Wang, Ernest S. Cohen, Rene Antonio Vega, Sharvil A. Nanavati
  • Patent number: 7363463
    Abstract: A method of virtualizing memory through shadow page tables that cache translations from multiple guest address spaces in a virtual machine includes a software version of a hardware tagged translation look-aside buffer. Edits to guest page tables are detected by intercepting the creation of guest-writable mappings to guest page tables with translations cached in shadow page tables. The affected cached translations are marked as stale and purged upon an address space switch or an indiscriminate flush of translations by the guest. Thereby, non-stale translations remain cached but stale translations are discarded. The method includes tracking the guest-writable mappings to guest page tables, deferring discovery of such mappings to a guest page table for the first time until a purge of all cached translations when the number of untracked guest page tables exceeds a threshold, and sharing shadow page tables between shadow address spaces and between virtual processors.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: April 22, 2008
    Assignee: Microsoft Corporation
    Inventors: John Te-Jui Sheu, David S. Bailey, Eric P. Traut, Rene Antonio Vega