Abstract: To protect memory cards, such as SD type cards, and similar devices from Electrostatic Discharge (ESD), the input pads of the device include points along their edges that are aligned with correspond points on a conductive frame structure mounted adjacent the input pad to form a spark gap. The input pads are connected to a memory controller or other ASIC over signal lines that include a diode located between the input pad and the ASIC and a resistance located between the input pad and the diode. The resistance and diode are selected such that an ESD event at an input pad triggers a discharge across the spark gap before it is transmitted on to the ASIC, while also allowing a high data rate for signals along the signal line.

Abstract: The present disclosure generally relates to apparatuses and methods for transmission line termination. In one embodiment an apparatus includes a stack of uniform memory dies and a storage controller. Each uniform memory die in the stack of uniform memory dies couples to a transmission line in series through wire bonds to form a transmission path. Each memory die includes an on-die termination resistance circuit connected to the transmission line. The on-die termination resistance circuit provides a minimum termination resistance. The storage controller addresses a target uniform memory die of the stack of uniform memory dies for an operation. The storage controller enables the on-die termination resistance circuits of a plurality of uniform memory dies along the transmission path. The storage controller transmits a data signal for the operation to the target uniform memory die with the on-die termination resistance circuit enabled for the plurality of uniform memory dies.

Abstract: An active termination circuit comprising an input node connected to a transmission line, a first transistor, and a second transistor. The transmission line supplies a signal to the input node. The first transistor is diode connected between a high voltage supply and the input node. The first transistor terminates the signal when the signal is at a low logic level. The second transistor is diode connected between the input node and a low voltage supply. The second transistor terminates the signal when the signal is at a high logic level.

Abstract: A circuit interconnect for high bandwidth and high die-count memory stacks. The circuit interconnect may include a first ground trace, a first signal trace, a second ground trace, and a second signal trace. The first ground trace may reside in a first layer of a multilayer printed circuit board. The first signal trace may be positioned adjacent to the first ground trace within the first layer. The second ground trace may reside within a second layer of the multilayer printed circuit board. The second signal trace may be positioned adjacent to the second ground trace within the second layer.

Abstract: An active termination circuit comprising an input node connected to a transmission line, a first transistor, and a second transistor. The transmission line supplies a signal to the input node. The first transistor is diode connected between a high voltage supply and the input node. The first transistor terminates the signal when the signal is at a low logic level. The second transistor is diode connected between the input node and a low voltage supply. The second transistor terminates the signal when the signal is at a high logic level.

Abstract: A circuit interconnect for high bandwidth and high die-count memory stacks. The circuit interconnect may include a first ground trace, a first signal trace, a second ground trace, and a second signal trace. The first ground trace may reside in a first layer of a multilayer printed circuit board. The first signal trace may be positioned adjacent to the first ground trace within the first layer. The second ground trace may reside within a second layer of the multilayer printed circuit board. The second signal trace may be positioned adjacent to the second ground trace within the second layer.

Abstract: The disclosed apparatuses and method provide transmission line termination. An apparatus include a stack of uniform memory dies and a storage controller. Each uniform memory die in the stack of uniform memory dies couples to a transmission line in series through wire bonds to form a transmission path. Each memory die includes an on-die termination resistance circuit connected to the transmission line. The on-die termination resistance circuit provides a minimum termination resistance. The storage controller addresses a target uniform memory die of the for an operation. The storage controller enables the on-die termination resistance circuits of a plurality of uniform memory dies along the transmission path. The storage controller transmits a data signal for the operation to the target uniform memory die with the on-die termination resistance circuit enabled for the plurality of uniform memory dies.

Abstract: To protect memory cards, such as SD type cards, and similar devices from Electrostatic Discharge (ESD), the input pads of the device include points along their edges that are aligned with correspond points on a conductive frame structure mounted adjacent the input pad to form a spark gap. The input pads are connected to a memory controller or other ASIC over signal lines that include a diode located between the input pad and the ASIC and a resistance located between the input pad and the diode. The resistance and diode are selected such that an ESD event at an input pad triggers a discharge across the spark gap before it is transmitted on to the ASIC, while also allowing a high data rate for signals along the signal line.

Abstract: A hard disk drive has a gas-bearing slider supporting a write head with an electrically conductive structure, like a spin-torque oscillator (STO), in the write gap, and dual independent interface voltage control (IVC) circuitry coupled to elements on the slider. A first IVC circuitry provides a bias voltage to the slider body to assure substantially zero electrical potential between the slider body and the disk to minimize slider-disk contact and lubrication pick-up. A second IVC circuitry operates independently of the first IVC circuitry and provides a bias voltage to the electrically conductive structure region to assure a negative potential of the electrically conductive structure region relative to the disk to minimize degradation of the slider overcoat and thus oxidation of the electrically conductive structure.

Abstract: An apparatus may include a controller die and a group of dies that communicate with each other via a transmission line. The transmission line includes a first portion integrated with a printed circuit board, and a second portion that includes a plurality of wire bonds bonded to input/output pads of the group of dies. The transmission line further includes a resistor circuit connected in series with the first portion and the second portion. The resistor circuit has a resistance value that provides reduced reflection coefficients over the transmission line between the first portion and the second portion. An on-die termination resistor circuit on the controller side is removed, with the inclusion of the resistor circuit.

Abstract: An apparatus includes a controller die and a group of dies that communicate with each other via a transmission line. Less than all of the dies of the group includes a respective on-die termination resistance circuit coupled to the transmission line. In some embodiments, one of the dies that includes an on-die termination resistance circuit is an end die of the group. In particular embodiments, the end die is the only die of the group that includes an on-die termination resistance circuit coupled to the transmission line. Transmission frequencies or data rates may be increased without degrading signal quality by removing capacitance associated with on-die termination resistance circuits from at least one of the dies of the group.

Abstract: An apparatus includes a controller die and a group of dies that communicate with each other via a transmission line. Less than all of the dies of the group includes a respective on-die termination resistance circuit coupled to the transmission line. In some embodiments, one of the dies that includes an on-die termination resistance circuit is an end die of the group. In particular embodiments, the end die is the only die of the group that includes an on-die termination resistance circuit coupled to the transmission line. Transmission frequencies or data rates may be increased without degrading signal quality by removing capacitance associated with on-die termination resistance circuits from at least one of the dies of the group.

Abstract: An apparatus may include a controller die and a group of dies that communicate with each other via a transmission line. The transmission line includes a first portion integrated with a printed circuit board, and a second portion that includes a plurality of wire bonds bonded to input/output pads of the group of dies. The transmission line further includes a resistor circuit connected in series with the first portion and the second portion. The resistor circuit has a resistance value that provides reduced reflection coefficients over the transmission line between the first portion and the second portion. An on-die termination resistor circuit on the controller side is removed, with the inclusion of the resistor circuit.

Abstract: An apparatus comprising memory having at least one memory die is disclosed. The apparatus may comprises a memory controller. A data bus is coupled to the controller and the memory. A supplemental inductor is coupled to the data bus.

Abstract: An apparatus may include a controller die configured to communicate with a plurality of dies via a transmission line. The controller die may be configured to transmit a signal on the transmission line to a target die of the plurality of dies, or the target die may transmit a signal on the transmission line. The transmission may be dependent on an end die of the plurality of dies setting an end-die termination resistance to a low level. In situations where the target memory is receiving the signal, the target die may set target an on-die termination resistance to a high level. In situations where the target memory die is transmitting the signal, the target die may set an on-die termination resistance to a low level.

Abstract: An active low-power termination circuit includes a first leg of a pair of transistors connected in series between the high supply level and ground, where the termination input is at a node between the transistors of the first node. A second leg uses a feed forward mechanism to control the voltage levels on the control gates of the transistors of the first leg. The second leg includes a second pair diode connected transistors, each of which is has its control gate connected to the control gate of the corresponding transistor in the first leg. A variable current source connected in series with the transistors of the second leg and is controlled by the output of a difference amplifier that has one input connect to an intermediate node of the second leg and a second input connected to a reference level intermediate to the high supply level and ground.

Abstract: An apparatus may include a controller die configured to communicate with a plurality of dies via a transmission line. The controller die may be configured to transmit a signal on the transmission line to a target die of the plurality of dies, or the target die may transmit a signal on the transmission line. The transmission may be dependent on an end die of the plurality of dies setting an end-die termination resistance to a low level. In situations where the target memory is receiving the signal, the target die may set target an on-die termination resistance to a high level. In situations where the target memory die is transmitting the signal, the target die may set an on-die termination resistance to a low level.

Abstract: A two-dimensional magnetic recording (TDMR) disk drive has a gas-bearing slider that includes first and second sensors with a first cross-track spacing electrically coupled to a first magnetic shield, and third and fourth sensors with a different cross-track spacing electrically coupled to a second magnetic shield. The different spacings results in the first and third sensors and the second and fourth sensors having a cross-track spacing to accommodate for the effect of head skew. Each sensor is connected to an associated amplifier by a suspension trace and a common trace connected to its associated shield. Switching circuitry selects either the first and third amplifiers or the second and fourth amplifiers as the active pair depending on the radial location where the data is to be read. Thus the appropriate pair of sensors are aligned with the data tracks despite the presence of high head skew.

Abstract: A multiple-segment transmission line in a hard disk drive enables a wider optimization range of the slope, duration and amplitude of the transmission line overshoot (TLO) wave shape. There is a first segment with two traces for connection to the write driver circuitry, an end segment with two traces for connection to the write head and at least two intermediate segments. The number of traces in a segment is different from the number of traces in the segments to which the segment is immediately connected. There is an even number of traces in each segment and the traces in each segment are interleaved. The number of segments and the number of traces in each segment can be selected to achieve the desired impedance levels for the different segments to achieve the desired wave shape for the TLO. All of the traces on the transmission line are preferably coplanar.

Abstract: A multiple-segment transmission line in a hard disk drive enables a wider optimization range of the slope, duration and amplitude of the transmission line overshoot (TLO) wave shape. There is a first segment with two traces for connection to the write driver circuitry, an end segment with two traces for connection to the write head and at least two intermediate segments. The number of traces in a segment is different from the number of traces in the segments to which the segment is immediately connected. There is an even number of traces in each segment and the traces in each segment are interleaved. The number of segments and the number of traces in each segment can be selected to achieve the desired impedance levels for the different segments to achieve the desired wave shape for the TLO. All of the traces on the transmission line are preferably coplanar.