Abstract: Circuits, systems, and methods for discharging loads are provided. One circuit includes a node coupled to a voltage source, a capacitor, a source-follower device coupled between the node and the capacitor, and a current source coupled to the capacitor. The source-follower device is configured to switchably couple the capacitor to the node to discharge the voltage source and the current source is configured to discharge the capacitor. One system includes the above circuit coupled to a memory device such that the circuit is configured to discharge voltage from the memory device. A method includes discharging, via a capacitor coupled to the memory device, a high voltage from the memory device and discharging, via a current source coupled to the capacitor, the high voltage from the capacitor. The capacitor is configured to discharge the high voltage within a predetermined range of time.

Abstract: Apparatus, systems, and methods for providing high voltage to memory devices are provided. One apparatus includes a low voltage input and a two-rail level shifting. The two-rail level shifting is configured to increase the low voltage or to decrease the low voltage to an amount that is less than or equal to a ground potential based on the amount of the low voltage. A system includes a low voltage input for receiving a voltage and a two-rail level shifting coupled to the low voltage input. The two-rail level shifting is configured to increase the voltage to a positive voltage if the voltage is equal to a ground potential and decrease the voltage to a negative voltage if the voltage is greater than the ground potential. One method includes receiving a voltage, modifying the voltage to generate one of a plurality of output voltages, and providing the output voltage to a memory device.

Abstract: A method and apparatus to program data into a row of a non-volatile memory array and verify, internally to the non-volatile memory array, that the data was successfully programmed. The verification includes comparing the programmed data from the row of the non-volatile memory array to data in the plurality of high voltage page latches that were used to program the row.