Patents by Inventor John Torvik

John Torvik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090115052
    Abstract: A hybrid electronic device incorporating both Si and non-Si semiconductor components, utilizing SiC, diamond, or another highly thermally conductive material as an underlying heat spreader. The hybrid electronic device is comprised of some combination of components fabricated in: (1) the underlying heat spreader itself; (2) a thin Si layer attached to the heat spreader via wafer bonding; and/or (3) a discrete semiconductor electronics die soldered to the heat spreader.
    Type: Application
    Filed: May 27, 2008
    Publication date: May 7, 2009
    Applicant: Astralux, Inc.
    Inventors: Randolph E. Treece, Steven Gregory Whipple, John Torvik
  • Publication number: 20050260821
    Abstract: Methods of constructing silicon carbide semiconductor devices in a self-aligned manner. According to one aspect of the invention, the method may include forming a mesa structure in a multi-layer laminate including at least a first and second layer of silicon carbide material. The mesa structure may then be utilized in combination with at least one planarization step to construct devices in a self-aligned manner. According to another aspect of the present invention, the mesa structure may be formed subsequent to an ion implantation and anneal steps to construct devices in a self-aligned manner. According to another aspect of the present invention, a high temperature mask capable of withstanding the high temperatures of the anneal process may be utilized to form devices in a self-aligned manner.
    Type: Application
    Filed: November 24, 2004
    Publication date: November 24, 2005
    Inventors: Bart Van Zeghbroeck, John Torvik
  • Publication number: 20050224808
    Abstract: Silicon carbide semiconductor devices having regrown layers and methods of fabricating the same in a self-aligned manner. According to one aspect of the invention, the method includes growing at least one layer of silicon carbide on a substrate, removing the device from a growth chamber to perform at least one processing step, and regrowing another layer of silicon carbide on the at least one layer. According to one embodiment of the invention, the regrown layer may be a heavily doped contact layer for the formation of low resistivity ohmic contacts.
    Type: Application
    Filed: May 19, 2005
    Publication date: October 13, 2005
    Inventors: Bart Van Zeghbroeck, John Torvik
  • Publication number: 20050082554
    Abstract: A direct-wafer-bonded, double heterojunction, light emitting semiconductor device includes an ordered array of quantum dots made of one or more indirect band gap materials selected from a group consisting of Si, Ge, SiGe, SiGeC, 3C—SiC, and hexagonal SiC, wherein the quantum dots are sandwiched between an n-type semiconductor cladding layer selected from a group consisting of SiC, 3C—SiC, 4H—SiC, 6H—SiC and diamond, and a p-type semiconductor cladding layer selected from a group consisting of SiC, 3C—SiC, 4H—SiC, 6H—SiC and diamond. A Ni contact is provided for the n-type cladding layer. An Al, a Ti or an Al/Ti alloy contact is provided for the p-type cladding layer. The quantum dots have a thickness that is no greater than about 250 Angstroms, a width that is no greater than about 200 Angstroms, and a center-to-center spacing that is in the range of from about 10 Angstroms to about 1000 Angstroms.
    Type: Application
    Filed: May 6, 2003
    Publication date: April 21, 2005
    Inventor: John Torvik
  • Publication number: 20040082191
    Abstract: The invention includes methods for precisely and accurately etching layers of wide bandgap semiconductor material. According to one aspect of the invention, the method includes providing a multi-layer laminate including at least a first and second layer of wide bandgap semiconductor material, measuring a first conductance of the first layer of semiconductor material, partially etching the first layer of semiconductor material a first amount, measuring a second conductance of the first layer of semiconductor material etched the first amount, and utilizing the first and second measured conductance to determine a time required to etch the first layer of semiconductor material a second amount.
    Type: Application
    Filed: July 30, 2003
    Publication date: April 29, 2004
    Inventors: Bart J. Van Zeghbroeck, Ivan Perez, John Torvik