Patents by Inventor John Traver

John Traver has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12531732
    Abstract: A method and apparatus for storing keys in a key storage block includes processing a key request. A first key is allocated based upon the key request. The first key is stored in the key storage block, wherein the first key is of a first size and includes a first rule.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: January 20, 2026
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Norman Vernon Douglas Stewart, Mihir Shaileshbhai Doctor, Omar Fakhri Ahmed, Hemaprabhu Jayanna, John Traver
  • Publication number: 20250335271
    Abstract: Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.
    Type: Application
    Filed: July 3, 2025
    Publication date: October 30, 2025
    Inventors: John Traver, Jay R. Shoen
  • Patent number: 12413568
    Abstract: A method and system for distributing keys in a key distribution system includes receiving a connection for communication from a first component. A determination is made whether the first component requires a key be generated and distributed. Based upon a security mode for the communication, the key generated and distributed to the first component.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: September 9, 2025
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Norman Vernon Douglas Stewart, Mihir Shaileshbhai Doctor, Omar Fakhri Ahmed, Hemaprabhu Jayanna, John Traver
  • Patent number: 12353928
    Abstract: Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.
    Type: Grant
    Filed: April 23, 2024
    Date of Patent: July 8, 2025
    Assignee: Micron Technology, Inc.
    Inventors: John Traver, Jay R. Shoen
  • Publication number: 20240272967
    Abstract: Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.
    Type: Application
    Filed: April 23, 2024
    Publication date: August 15, 2024
    Inventors: John Traver, Jay R. Shoen
  • Patent number: 11989600
    Abstract: Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: May 21, 2024
    Assignee: Micron Technology, Inc.
    Inventors: John Traver, Jay R. Shoen
  • Publication number: 20240113875
    Abstract: A method and apparatus for storing keys in a key storage block includes processing a key request. A first key is allocated based upon the key request. The first key is stored in the key storage block, wherein the first key is of a first size and includes a first rule.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Norman Vernon Douglas Stewart, Mihir Shaileshbhai Doctor, Omar Fakhri Ahmed, Hemaprabhu Jayanna, John Traver
  • Publication number: 20240106813
    Abstract: A method and system for distributing keys in a key distribution system includes receiving a connection for communication from a first component. A determination is made whether the first component requires a key be generated and distributed. Based upon a security mode for the communication, the key generated and distributed to the first component.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 28, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Norman Vernon Douglas Stewart, Mihir Shaileshbhai Doctor, Omar Fakhri Ahmed, Hemaprabhu Jayanna, John Traver
  • Patent number: 11726669
    Abstract: Methods, systems, and devices for coherency locking are described in which different types of writes have different coherency locking schemes. The types of writes can be associated with different sources of write commands, such as external commands from a host system or internal commands from a garbage collection procedure. Coherency locking can be performed for external write commands received from a host system, while coherency locking is not performed for internal write commands. If an internal write is received for data that has been previously written at a prior location, a write to one or more physical memory devices can be performed and, once an acknowledgment is received that the write is complete, an update to a mapping table with the new location of the data is performed.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: August 15, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Yun Li, John Traver
  • Patent number: 11726716
    Abstract: Methods, systems, and devices for internal commands for access operations are described. A memory sub-system can receive a request to perform an access operation. A first core of the memory sub-system can generate an internal command for performing the access operation. The internal command can include information for storing in a reference queue of the memory sub-system and an identification of a command entry of the reference queue. The first core can issue the internal command to perform the access operation and a second core of the memory sub-system can store the information in the command entry of the reference queue.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: August 15, 2023
    Assignee: Micron Technology, Inc.
    Inventors: John Traver, Ning Zhao, Tom V. Geukens, Yun Li
  • Publication number: 20230014975
    Abstract: Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.
    Type: Application
    Filed: September 15, 2022
    Publication date: January 19, 2023
    Inventors: John Traver, Jay R. Shoen
  • Patent number: 11474885
    Abstract: Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: October 18, 2022
    Assignee: Micron Technology, Inc.
    Inventors: John Traver, Jay R. Shoen
  • Publication number: 20220283713
    Abstract: Methods, systems, and devices for coherency locking are described in which different types of writes have different coherency locking schemes. The types of writes can be associated with different sources of write commands, such as external commands from a host system or internal commands from a garbage collection procedure. Coherency locking can be performed for external write commands received from a host system, while coherency locking is not performed for internal write commands. If an internal write is received for data that has been previously written at a prior location, a write to one or more physical memory devices can be performed and, once an acknowledgment is received that the write is complete, an update to a mapping table with the new location of the data is performed.
    Type: Application
    Filed: March 24, 2022
    Publication date: September 8, 2022
    Inventors: Yun Li, John Traver
  • Patent number: 11287987
    Abstract: Methods, systems, and devices for coherency locking are described in which different types of writes have different coherency locking schemes. The types of writes can be associated with different sources of write commands, such as external commands from a host system or internal commands from a garbage collection procedure. Coherency locking can be performed for external write commands received from a host system, while coherency locking is not performed for internal write commands. If an internal write is received for data that has been previously written at a prior location, a write to one or more physical memory devices can be performed and, once an acknowledgment is received that the write is complete, an update to a mapping table with the new location of the data is performed.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: March 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yun Li, John Traver
  • Publication number: 20210405929
    Abstract: Methods, systems, and devices for internal commands for access operations are described. A memory sub-system can receive a request to perform an access operation. A first core of the memory sub-system can generate an internal command for performing the access operation. The internal command can include information for storing in a reference queue of the memory sub-system and an identification of a command entry of the reference queue. The first core can issue the internal command to perform the access operation and a second core of the memory sub-system can store the information in the command entry of the reference queue.
    Type: Application
    Filed: September 8, 2021
    Publication date: December 30, 2021
    Inventors: John Traver, Ning Zhao, Tom V. Geukens, Yun LI
  • Publication number: 20210311811
    Abstract: Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.
    Type: Application
    Filed: April 7, 2020
    Publication date: October 7, 2021
    Inventors: John Traver, Jay R. Shoen
  • Patent number: 11137943
    Abstract: Methods, systems, and devices for internal commands for access operations are described. A memory sub-system can receive a request to perform an access operation. A first core of the memory sub-system can generate an internal command for performing the access operation. The internal command can include information for storing in a reference queue of the memory sub-system and an identification of a command entry of the reference queue. The first core can issue the internal command to perform the access operation and a second core of the memory sub-system can store the information in the command entry of the reference queue.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John Traver, Ning Zhao, Tom V. Geukens, Yun Li
  • Publication number: 20210278995
    Abstract: Methods, systems, and devices for internal commands for access operations are described. A memory sub-system can receive a request to perform an access operation. A first core of the memory sub-system can generate an internal command for performing the access operation. The internal command can include information for storing in a reference queue of the memory sub-system and an identification of a command entry of the reference queue. The first core can issue the internal command to perform the access operation and a second core of the memory sub-system can store the information in the command entry of the reference queue.
    Type: Application
    Filed: March 4, 2020
    Publication date: September 9, 2021
    Inventors: John Traver, Ning Zhao, Tom V. Geukens, Yun Li
  • Publication number: 20210278976
    Abstract: Methods, systems, and devices for coherency locking are described in which different types of writes have different coherency locking schemes. The types of writes can be associated with different sources of write commands, such as external commands from a host system or internal commands from a garbage collection procedure. Coherency locking can be performed for external write commands received from a host system, while coherency locking is not performed for internal write commands. If an internal write is received for data that has been previously written at a prior location, a write to one or more physical memory devices can be performed and, once an acknowledgment is received that the write is complete, an update to a mapping table with the new location of the data is performed.
    Type: Application
    Filed: March 4, 2020
    Publication date: September 9, 2021
    Inventors: Yun Li, John Traver
  • Publication number: 20070112880
    Abstract: In one example, a synchronization server includes logic operable to engage in a first synchronization session with a client device, wherein client modifications and server modifications may be exchanged based, at least in part, on synchronization data stored locally. The synchronization server further includes logic operable to initiate a query of a remote database (e.g., having data associated with the synchronization data) to determine differences between the synchronization data stored locally and associated data stored remotely. The synchronization server is further operable to initiate an exchange of further server modifications based on the differences between the synchronization data stored locally and the associated data stored remotely. In one example, the server may engage in a second synchronization session with the client device to update the client device with differences to the synchronization data stored locally and the remote database.
    Type: Application
    Filed: November 14, 2005
    Publication date: May 17, 2007
    Inventors: Lie Yang, John Traver, Venkatachary Srinivasan, Marco Boerries