Patents by Inventor John Traver
John Traver has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12531732Abstract: A method and apparatus for storing keys in a key storage block includes processing a key request. A first key is allocated based upon the key request. The first key is stored in the key storage block, wherein the first key is of a first size and includes a first rule.Type: GrantFiled: September 29, 2022Date of Patent: January 20, 2026Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Norman Vernon Douglas Stewart, Mihir Shaileshbhai Doctor, Omar Fakhri Ahmed, Hemaprabhu Jayanna, John Traver
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Publication number: 20250335271Abstract: Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.Type: ApplicationFiled: July 3, 2025Publication date: October 30, 2025Inventors: John Traver, Jay R. Shoen
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Patent number: 12413568Abstract: A method and system for distributing keys in a key distribution system includes receiving a connection for communication from a first component. A determination is made whether the first component requires a key be generated and distributed. Based upon a security mode for the communication, the key generated and distributed to the first component.Type: GrantFiled: September 28, 2022Date of Patent: September 9, 2025Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Norman Vernon Douglas Stewart, Mihir Shaileshbhai Doctor, Omar Fakhri Ahmed, Hemaprabhu Jayanna, John Traver
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Patent number: 12353928Abstract: Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.Type: GrantFiled: April 23, 2024Date of Patent: July 8, 2025Assignee: Micron Technology, Inc.Inventors: John Traver, Jay R. Shoen
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Publication number: 20240272967Abstract: Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.Type: ApplicationFiled: April 23, 2024Publication date: August 15, 2024Inventors: John Traver, Jay R. Shoen
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Patent number: 11989600Abstract: Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.Type: GrantFiled: September 15, 2022Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventors: John Traver, Jay R. Shoen
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Publication number: 20240113875Abstract: A method and apparatus for storing keys in a key storage block includes processing a key request. A first key is allocated based upon the key request. The first key is stored in the key storage block, wherein the first key is of a first size and includes a first rule.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Norman Vernon Douglas Stewart, Mihir Shaileshbhai Doctor, Omar Fakhri Ahmed, Hemaprabhu Jayanna, John Traver
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Publication number: 20240106813Abstract: A method and system for distributing keys in a key distribution system includes receiving a connection for communication from a first component. A determination is made whether the first component requires a key be generated and distributed. Based upon a security mode for the communication, the key generated and distributed to the first component.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Norman Vernon Douglas Stewart, Mihir Shaileshbhai Doctor, Omar Fakhri Ahmed, Hemaprabhu Jayanna, John Traver
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Patent number: 11726669Abstract: Methods, systems, and devices for coherency locking are described in which different types of writes have different coherency locking schemes. The types of writes can be associated with different sources of write commands, such as external commands from a host system or internal commands from a garbage collection procedure. Coherency locking can be performed for external write commands received from a host system, while coherency locking is not performed for internal write commands. If an internal write is received for data that has been previously written at a prior location, a write to one or more physical memory devices can be performed and, once an acknowledgment is received that the write is complete, an update to a mapping table with the new location of the data is performed.Type: GrantFiled: March 24, 2022Date of Patent: August 15, 2023Assignee: Micron Technology, Inc.Inventors: Yun Li, John Traver
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Patent number: 11726716Abstract: Methods, systems, and devices for internal commands for access operations are described. A memory sub-system can receive a request to perform an access operation. A first core of the memory sub-system can generate an internal command for performing the access operation. The internal command can include information for storing in a reference queue of the memory sub-system and an identification of a command entry of the reference queue. The first core can issue the internal command to perform the access operation and a second core of the memory sub-system can store the information in the command entry of the reference queue.Type: GrantFiled: September 8, 2021Date of Patent: August 15, 2023Assignee: Micron Technology, Inc.Inventors: John Traver, Ning Zhao, Tom V. Geukens, Yun Li
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Publication number: 20230014975Abstract: Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.Type: ApplicationFiled: September 15, 2022Publication date: January 19, 2023Inventors: John Traver, Jay R. Shoen
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Patent number: 11474885Abstract: Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.Type: GrantFiled: April 7, 2020Date of Patent: October 18, 2022Assignee: Micron Technology, Inc.Inventors: John Traver, Jay R. Shoen
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Publication number: 20220283713Abstract: Methods, systems, and devices for coherency locking are described in which different types of writes have different coherency locking schemes. The types of writes can be associated with different sources of write commands, such as external commands from a host system or internal commands from a garbage collection procedure. Coherency locking can be performed for external write commands received from a host system, while coherency locking is not performed for internal write commands. If an internal write is received for data that has been previously written at a prior location, a write to one or more physical memory devices can be performed and, once an acknowledgment is received that the write is complete, an update to a mapping table with the new location of the data is performed.Type: ApplicationFiled: March 24, 2022Publication date: September 8, 2022Inventors: Yun Li, John Traver
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Patent number: 11287987Abstract: Methods, systems, and devices for coherency locking are described in which different types of writes have different coherency locking schemes. The types of writes can be associated with different sources of write commands, such as external commands from a host system or internal commands from a garbage collection procedure. Coherency locking can be performed for external write commands received from a host system, while coherency locking is not performed for internal write commands. If an internal write is received for data that has been previously written at a prior location, a write to one or more physical memory devices can be performed and, once an acknowledgment is received that the write is complete, an update to a mapping table with the new location of the data is performed.Type: GrantFiled: March 4, 2020Date of Patent: March 29, 2022Assignee: Micron Technology, Inc.Inventors: Yun Li, John Traver
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Publication number: 20210405929Abstract: Methods, systems, and devices for internal commands for access operations are described. A memory sub-system can receive a request to perform an access operation. A first core of the memory sub-system can generate an internal command for performing the access operation. The internal command can include information for storing in a reference queue of the memory sub-system and an identification of a command entry of the reference queue. The first core can issue the internal command to perform the access operation and a second core of the memory sub-system can store the information in the command entry of the reference queue.Type: ApplicationFiled: September 8, 2021Publication date: December 30, 2021Inventors: John Traver, Ning Zhao, Tom V. Geukens, Yun LI
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Publication number: 20210311811Abstract: Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.Type: ApplicationFiled: April 7, 2020Publication date: October 7, 2021Inventors: John Traver, Jay R. Shoen
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Patent number: 11137943Abstract: Methods, systems, and devices for internal commands for access operations are described. A memory sub-system can receive a request to perform an access operation. A first core of the memory sub-system can generate an internal command for performing the access operation. The internal command can include information for storing in a reference queue of the memory sub-system and an identification of a command entry of the reference queue. The first core can issue the internal command to perform the access operation and a second core of the memory sub-system can store the information in the command entry of the reference queue.Type: GrantFiled: March 4, 2020Date of Patent: October 5, 2021Assignee: Micron Technology, Inc.Inventors: John Traver, Ning Zhao, Tom V. Geukens, Yun Li
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Publication number: 20210278995Abstract: Methods, systems, and devices for internal commands for access operations are described. A memory sub-system can receive a request to perform an access operation. A first core of the memory sub-system can generate an internal command for performing the access operation. The internal command can include information for storing in a reference queue of the memory sub-system and an identification of a command entry of the reference queue. The first core can issue the internal command to perform the access operation and a second core of the memory sub-system can store the information in the command entry of the reference queue.Type: ApplicationFiled: March 4, 2020Publication date: September 9, 2021Inventors: John Traver, Ning Zhao, Tom V. Geukens, Yun Li
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Publication number: 20210278976Abstract: Methods, systems, and devices for coherency locking are described in which different types of writes have different coherency locking schemes. The types of writes can be associated with different sources of write commands, such as external commands from a host system or internal commands from a garbage collection procedure. Coherency locking can be performed for external write commands received from a host system, while coherency locking is not performed for internal write commands. If an internal write is received for data that has been previously written at a prior location, a write to one or more physical memory devices can be performed and, once an acknowledgment is received that the write is complete, an update to a mapping table with the new location of the data is performed.Type: ApplicationFiled: March 4, 2020Publication date: September 9, 2021Inventors: Yun Li, John Traver
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Publication number: 20070112880Abstract: In one example, a synchronization server includes logic operable to engage in a first synchronization session with a client device, wherein client modifications and server modifications may be exchanged based, at least in part, on synchronization data stored locally. The synchronization server further includes logic operable to initiate a query of a remote database (e.g., having data associated with the synchronization data) to determine differences between the synchronization data stored locally and associated data stored remotely. The synchronization server is further operable to initiate an exchange of further server modifications based on the differences between the synchronization data stored locally and the associated data stored remotely. In one example, the server may engage in a second synchronization session with the client device to update the client device with differences to the synchronization data stored locally and the remote database.Type: ApplicationFiled: November 14, 2005Publication date: May 17, 2007Inventors: Lie Yang, John Traver, Venkatachary Srinivasan, Marco Boerries