Abstract: The subject matter of this specification can be implemented in, among other things, a computer-implemented user interface method including displaying on a touchscreen display a representation of a keyboard defining a top edge and a bottom edge, and a content area adjacent to the keyboard. The method further includes receiving a user dragging input having motion directed to the bottom edge of the keyboard. The method further includes removing the keyboard from the touchscreen display and expanding the content area to an area previously occupied by the keyboard.

Abstract: Automatic testing for control valves is provided for diagnosing of actuators, including actuators not equipped with analog or discrete position transmitters. A valve controller confirms steady-state conditions for a turbo-compressor system that includes a control valve in a first position and sends, to an actuator for the control valve, a signal to initiate a partial valve stroke to move the control valve away from the first position. The valve controller receives feedback signals from sensors in the turbo-compressor system and monitors the feedback signals for a change from the steady-state conditions. When the monitoring detects a change from the steady-state conditions within a defined time period, the valve controller sends, to the actuator, a signal to return the control valve to the first position. When the monitoring does not detect a change from the steady-state conditions within the defined time period, the valve controller generates an alarm signal.

Abstract: Various embodiments are described herein for the fabrication enzyme degradable hydrogels useful as payload delivery systems. More particularly, embodiments disclosed herein relate to enzyme-degradable hydrogel systems comprising a crosslinkable polymer, such as a chemically-modified biopolymer, for example, chemically-modified gelatin, the hydrogel formed by a method comprising sequential physical and chemical crosslinking steps, for delivery of various payloads. Enzymes may be selected and administered to tune the release profile of the hydrogel. The payload can be, but not limited to, drugs, markers, cells, or these members encapsulated within another drug delivery such as a nanoparticle, or liposome. The hydrogel system can also be combined with another device such as a contact lens or bandage for wound healing.

Abstract: Automatic testing for control valves is provided for diagnosing of actuators, including actuators not equipped with analog or discrete position transmitters. A valve controller confirms steady-state conditions for a turbo-compressor system that includes a control valve in a first position and sends, to an actuator for the control valve, a signal to initiate a partial valve stroke to move the control valve away from the first position. The valve controller receives feedback signals from sensors in the turbo-compressor system and monitors the feedback signals for a change from the steady-state conditions. When the monitoring detects a change from the steady-state conditions within a defined time period, the valve controller sends, to the actuator, a signal to return the control valve to the first position. When the monitoring does not detect a change from the steady-state conditions within the defined time period, the valve controller generates an alarm signal.

Abstract: Methods and apparatus are described for efficiently performing EDA processing to arrive at a hardware definition for a varying fraction of a large circuit design. EDA processing is conducted targeting a pseudo hardware device with sufficient capacity to embody circuitry for the varying fraction, but substantially less than the true hardware target. The novel methods and apparatus may be beneficially employed to produce reconfiguration information for circuits that include programmable logic, for example.

Abstract: A memory configuration circuit is provided. The memory configuration circuit may be integrated into a programmable logic device (PLD) and as such, may be used to configure and reconfigure specific elements in the PLD. The memory configuration circuit includes a comparator circuit and a counter. The comparator circuit is coupled to receive two data words from two different memory configuration sources. The comparator circuit compares the two data words received before writing one of the data words to a configuration memory. One of the data words may be written to the configuration memory if the two data words compared are not equal. The counter increments the address of the memory configuration sources so that a next data word can be processed after the current data word is processed.

Abstract: Systems and methods of hierarchical circuit partitioning are provided. More specifically, the invention utilizes a sliding window which is moved over portions of a hierarchical structure representing a programmable logic device. The window includes some but not all containers of the hierarchical structure so that logic cells may be partitioned within the window. After the logic cells are partitioned in the window, the window is moved to a different location of the hierarchical structure. By utilizing a sliding window, the invention is able to recursively partition logic cells into portions of the hierarchical structure which increases the overall efficiency of the partitioning.

Abstract: A method for partitioning a group of cells in a network into a set of disjoint blocks of cells. The network is represented by a hierarchical graph with each level representing a hierarchy of resources, leaf nodes representing the blocks of cells, and edges representing interconnections between resources. A gain matrix is formed by combining a gain vector for each level of hierarchy for each possible move. Cells are moved between leaf nodes based on the gain matrix computed.

Abstract: A technique is disclosed for efficiently placing logic cells from an electronic design during an incremental recompile. This is accomplished by fixing in place as many logic cells as possible during the recompile procedure. To understand how this works, recognize than an "original electronic design" has already been fully compiled. Now, a user has made one or more changes to the original electronic design to produce a "changed electronic design." The disclosed technique fits the changed electronic design, during incremental recompile, without effecting too much of the logic previously fit during compilation of the original electronic design. Initially, a compiler attempts to fit logic cells of the changed portion of the electronic design onto available logic elements of the hardware device while confining logic cells from the unchanged portion of the changed electronic design to their original positions.

Abstract: Improved circuit partitioning methods are provided which combine the advantage of multiple starting positions of the random initial placement approach with the advantage of optimal starting positions of the greedy initial placement approach, by starting with greedy initial placement and modifying partitioning constraints on subsequent passes so that each pass begins in a new position, In addition, the partitioning goals of interconnection minimization and resource utilization efficiency may be prioritized according to a design goal by manipulating the manner in which partitioning constraints are changed during each partitioning pass. Furthermore a user may adjust the weight of the benefits for eliminating existing interconnections and the weight of the penalties for adding new interconnections in accordance with a design goal.

Abstract: A programmable logic array integrated circuit has a plurality of logic modules, each of which is programmable to perform any of several logic functions. One such function is the performance of one place of binary addition yielding a sum out signal and a carry out signal. In addition to a dedicated carry chain which conveys the carry out signal of each logic module to the carry in input of another predetermined logic module, circuitry is provided for allowing the carry out signal of each logic module to be alternatively routed through the more general interconnection circuitry of the device. This increases the flexibility of routing of the carry out signals, thereby increasing the flexibility of use of the integrated circuit. Improved circuitry for handling a carry in signal may also be provided in each logic module.