Abstract: A plurality of System On a Chip (SOC) integrated circuits, a media that intercouples the plurality of SOC integrated circuits to form at least one SOC LAN ring, and a routing address scheme. Each SOC integrated circuit includes at least one processor, a system bus, a memory controller, at least two Local Area Network (LAN) ports, and a receive channel selection block. The media intercouples the LAN ports of the plurality of SOC integrated circuits to form at least one SOC LAN ring. The routing address scheme serves in routing of data packets on the at least one SOC LAN ring. A routing address of the routing address scheme has a first portion that identifies a source SOC integrated circuit, a second portion that identifies a destination SOC integrated circuit, and a third portion that comprises a LAN address and data.

Abstract: A removable handswitch and electrode assembly for use with a forceps having opposing end effectors and a handle for effecting relative movement of the end effectors with respect to one another includes a housing having at least one portion which removably engages at least a portion of a mechanical forceps and a handswitch assembly disposed on the housing. A pair of electrodes is included which removably engage a distal end of the mechanical forceps such that the electrodes reside in opposing relation to one another. At least one electrode is adapted to connect to an electrosurgical generator through the handswitch assembly. At least one stop member is operatively associated with the electrodes and controls the distance between the opposing electrodes to affect a tissue seal.

Abstract: An output stage interface circuit (50) implemented on a P-substrate comprises a first substrate diffusion isolated main NMOS transistor (MN1) coupling a data output terminal (5) to a first rail (2) which is held at ground, and a second main PMOS transistor MP2 coupling the data output terminal (5) to a second rail (3) to which the power supply voltage VDD is applied. First and second data control signals on first and second data control lines (8) and (9) through first and second primary and secondary buffer circuits (11, 14, 12, 15) selectively operate the first main transistor MN1 and the second main transistor MP2 for determining the logic high and low states of the data output terminal (5).

Abstract: Tracing instruction flow in an integrated processor by defeaturing a cache hit into a cache miss to allow an instruction fetch to be made visible on a bus, which instruction would not have been made visible on the bus had the instruction fetch hit in the cache. The defeature activation is controlled by use of a defeature hit signal bit in a defeature register, and in which the bit may be programmed.

Abstract: A plurality of System On a Chip (SOC) integrated circuits, a media that intercouples the plurality of SOC integrated circuits to form at least one SOC LAN ring, and a routing address scheme. Each SOC integrated circuit includes at least one processor, a system bus, a memory controller, at least two Local Area Network (LAN) ports, and a receive channel selection block. The media intercouples the LAN ports of the plurality of SOC integrated circuits to form at least one SOC LAN ring. The routing address scheme serves in routing of data packets on the at least one SOC LAN ring. A routing address of the routing address scheme has a first portion that identifies a source SOC integrated circuit, a second portion that identifies a destination SOC integrated circuit, and a third portion that comprises a LAN address and data.