Abstract: A silicon carrier space transformer assembly includes one or more silicon structures, which provide space transformer scaling to permit interconnection for fine pitch input/output interconnections with a semiconductor die or wafer, and fine pitch test probe tips connected to the one or more silicon structures.

Abstract: A silicon carrier space transformer assembly includes one or more silicon structures, which provide space transformer scaling to permit interconnection for fine pitch input/output interconnections with a semiconductor die or wafer, and fine pitch test probe tips connected to the one or more silicon structures.

Abstract: A method for forming an integrated circuit assembly comprises forming first solder bumps on a first die, and forming a first structure comprising the first die, the first solder bumps, a first flux, and a first substratum. The first die is placed upon the first substratum. The first solder bumps are between the first die and the first substratum. The first flux holds the first die substantially flat and onto the first substratum.

Abstract: Techniques for modular chip fabrication are provided. In one aspect, a modular chip structure is provided. The modular chip structure comprises a substrate; a carrier platform attached to the substrate, the carrier platform comprising a plurality of conductive vias extending through the carrier platform; and a wiring layer on the carrier platform in contact with one or more of the conductive vias, wherein the wiring layer comprises one or more wiring levels and is configured to divide the carrier platform into a plurality of voltage islands; and chips, chip macros or at least one chip in combination with at least one chip macro assembled on the carrier platform.

Abstract: A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip stack; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chip stacks. The chip package further includes a cooling lid disposed above the chip stack providing additional cooling.

Abstract: A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chips or chip stacks.

Abstract: A semiconductor structure includes: at least one silicon surface wherein the surface can be a substrate, wafer or other device. The structure further includes at least one electronic circuit formed on each side of the at least one surface; and at least one conductive high aspect ratio through silicon via running through the at least one surface. Each through silicon via is fabricated from at least one etch step and includes: at least one thermal oxide dielectric for coating at least some of a sidewall of the through silicon via for a later etch stop in fabrication of the through silicon via.

Abstract: Techniques for modular chip fabrication are provided. In one aspect, a modular chip structure is provided. The modular chip structure comprises a substrate; a carrier platform attached to the substrate, the carrier platform comprising a plurality of conductive vias extending through the carrier platform; and a wiring layer on the carrier platform in contact with one or more of the conductive vias, wherein the wiring layer comprises one or more wiring levels and is configured to divide the carrier platform into a plurality of voltage islands; and chips, chip macros or at least one chip in combination with at least one chip macro assembled on the carrier platform.

Abstract: A silicon carrier structure for electronic packaging includes a base substrate, a silicon carrier substrate disposed on the base substrate, a memory chip disposed on the silicon carrier substrate, a microprocessor chip disposed on the silicon carrier substrate, an input/output chip disposed on the silicon carrier substrate, and a clocking chip disposed on the silicon carrier substrate.

Abstract: A silicon carrier space transformer assembly includes one or more silicon structures, which provide space transformer scaling to permit interconnection for fine pitch input/output interconnections with a semiconductor die or wafer, and fine pitch test probe tips connected to the one or more silicon structures.

Abstract: A silicon carrier structure for electronic packaging includes a base substrate, a silicon carrier substrate disposed on the base substrate, a memory chip disposed on the silicon carrier substrate, a microprocessor chip disposed on the silicon carrier substrate, an input/output chip disposed on the silicon carrier substrate, and a clocking chip disposed on the silicon carrier substrate.

Abstract: Techniques for modular chip fabrication are provided. In one aspect, a modular chip structure is provided. The modular chip structure comprises a substrate; a carrier platform attached to the substrate, the carrier platform comprising a plurality of conductive vias extending through the carrier platform; and a wiring layer on the carrier platform in contact with one or more of the conductive vias, wherein the wiring layer comprises one or more wiring levels and is configured to divide the carrier platform into a plurality of voltage islands; and chips, chip macros or at least one chip in combination with at least one chip macro assembled on the carrier platform.

Abstract: A silicon carrier space transformer assembly includes one or more silicon structures, which provide space transformer scaling to permit interconnection for fine pitch input/output interconnections with a semiconductor die or wafer, and fine pitch test probe tips connected to the one or more silicon structures.

Abstract: A method of testing integrated circuit chips. The method includes: attaching integrated circuit chips to an interposer of a temporary carrier, the carrier comprising: a substrate, a first interconnects on a bottom surface and a second array of interconnects on a top surface of the substrate, corresponding first and second interconnects electrically connected by wires in the substrate; the interposer, first pads on a top surface and a second pads on a bottom surface of the interposer, corresponding first and second pads electrically connected by wires in the interposer, and the second pads in physical and electrical contact with corresponding second interconnects; and the interposer including an interposer substrate comprising a same material as a substrate of the integrated circuit chip; connecting interconnects of the first array of interconnects to a tester; and testing the one or more integrated circuit chips.

Abstract: A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chips or chip stacks.

Abstract: A structure formation method. The method may include: attaching a substrate, a first interposer, a second interposer, and a first bridge together such that the first interposer is on and electrically connected to the substrate, the second interposer is on and electrically connected to the substrate, the first interposer comprises at least a first transistor, and the second interposer comprises at least a second transistor. The method may alternatively include: disposing both a first and second interposer on a substrate, wherein the first and second interposer are each electrically connected to the substrate; and electrically connecting a first bridge to the first and second interposers, wherein (i) the first bridge is in direct physical contact with the substrate or (ii) a bottom surface of the first bridge is within the substrate and below a top surface of the substrate.

Abstract: A method and apparatus for the formation of coplanar electrical interconnectors. Solder material is deposited onto a wafer, substrate, or other component of an electrical package using a complaint mold such that the terminal ends of the solder material being deposited, i.e., the ends opposite to those forming an attachment to the wafer, substrate, or other component of an electrical package are coplanar with one another. A complaint mold is used having one or more conduits for receiving solder material and having a compliant side and a planar side. The compliant side of the mold is positioned adjacent to the wafer, substrate, or other component of an electrical package allowing solder material to be deposited onto the surface thereof such that the planar side of the compliant mold provides coplanar interconnectors. An Injection Molded Solder (IMS) head can be used as the means for filling the conduits of the compliant mold of the present invention.

Abstract: A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chips or chip stacks.

Abstract: A structure formation method. The method may include: attaching a substrate, a first interposer, a second interposer, and a first bridge together such that the first interposer is on and electrically connected to the substrate, the second interposer is on and electrically connected to the substrate, the first interposer comprises at least a first transistor, and the second interposer comprises at least a second transistor. The method may alternatively include: disposing both a first and second interposer on a substrate, wherein the first and second interposer are each electrically connected to the substrate; and electrically connecting a first bridge to the first and second interposers, wherein (i) the first bridge is in direct physical contact with the substrate or (ii) a bottom surface of the first bridge is within the substrate and below a top surface of the substrate.

Abstract: A structure and a method for forming the same. The structure includes a substrate, a first interposer on the substrate, a second interposer on the substrate, and a first bridge. The first and second interposers are electrically connected to the substrate. The first bridge is electrically connected to the first and second interposers.