Abstract: The storage locations of a snoop filter are segregated into a number of groups, and some groups are associated with some processors in a system. When new data enter a cache line of a processor, one of the storage locations associated with the processor is selected for further operations.

Abstract: The storage locations of a snoop filter are segregated into a number of groups, and some groups are associated with some processors in a system. When new data enter a cache line of a processor, one of the storage locations associated with the processor is selected for further operations.

Abstract: The storage locations of a snoop filter are segregated into a number of groups, and some groups are associated with some processors in a system. When new data enter a cache line of a processor, one of the storage locations associated with the processor is selected for further operations.

Abstract: The storage locations of a snoop filter are segregated into a number of groups, and some groups are associated with some processors in a system. When new data enter a cache line of a processor, one of the storage locations associated with the processor is selected for further operations.

Abstract: A bus has a first set of data lines and a second set of data lines. In an embodiment, the bus has a selector circuit to count the number of data lines in the first set of data lines and second set of data lines that have a certain value and to select one set of data lines to be inverted based on the count. In an embodiment, the bus has a first inverter to invert the set of data lines selected and a second inverter to re-invert the set of data lines selected at a receiver based on the value of an added control line.

Abstract: A bus has a first set of data lines and a second set of data lines. In an embodiment, the bus has a selector circuit to count the number of data lines in the first set of data lines and second set of data lines that have a certain value and to select one set of data lines to be inverted based on the count. In an embodiment, the bus has a first inverter to invert the set of data lines selected and a second inverter to re-invert the set of data lines selected at a receiver based on the value of an added control line.

Abstract: A computer system including a slice-addressable multi-port memory array is disclosed. The slice-addressable multi-port memory array provides a mechanism for efficient data merging in a memory controller in accordance with an associated array of slice-enable bits. Each slice of the memory array is individually designated by a slice-enable bit, and only those slices of a word line enabled for writing that are designated by a slice-enable bit are modified during a write operation. In a subsequent write-merge operation, the slices of the word line enabled for writing that were not designated by slice-enable bits during the write operation are modified, and the slices that were modified during the preceding write operation are unaffected, thereby providing for efficient merger of data from the write operation and data from the write-merge operation in a single word line.

Abstract: A computer system having at least a first microprocessor for processing information and a first memory coupled to the first microprocessor via a first point-to-point interface. The first point-to-point interface provides communication of signals between the first microprocessor and the first memory irrespective of the phase of the signals received by either the first microprocessor or the first memory. The first point-to-point interface includes a first point-to-point circuit in the microprocessor for receiving the signals from the first memory. The first point-to-point circuit and the microprocessor comprise a single integrated circuit in some implemented embodiments, providing ease of construction and design of systems having a variety of topologies.