Patents by Inventor John Urbanski

John Urbanski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Pseudo least recently used replacement/allocation scheme in request agent affinitive set-associative snoop filter
    Publication number: 20060294314
    Abstract: The storage locations of a snoop filter are segregated into a number of groups, and some groups are associated with some processors in a system. When new data enter a cache line of a processor, one of the storage locations associated with the processor is selected for further operations.
    Type: Application
    Filed: June 28, 2005
    Publication date: December 28, 2006
    Inventors: Kai Cheng, David Lee, John Urbanski
  • Method and apparatus for encoding a bus to minimize simultaneous switching outputs effect
    Patent number: 6721918
    Abstract: A bus has a first set of data lines and a second set of data lines. In an embodiment, the bus has a selector circuit to count the number of data lines in the first set of data lines and second set of data lines that have a certain value and to select one set of data lines to be inverted based on the count. In an embodiment, the bus has a first inverter to invert the set of data lines selected and a second inverter to re-invert the set of data lines selected at a receiver based on the value of an added control line.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: April 13, 2004
    Assignee: Intel Corporation
    Inventors: Keith Self, John Urbanski
  • Method and apparatus for encoding a bus to minimize simultaneous switching outputs effect
    Publication number: 20020087936
    Abstract: A bus has a first set of data lines and a second set of data lines. In an embodiment, the bus has a selector circuit to count the number of data lines in the first set of data lines and second set of data lines that have a certain value and to select one set of data lines to be inverted based on the count. In an embodiment, the bus has a first inverter to invert the set of data lines selected and a second inverter to re-invert the set of data lines selected at a receiver based on the value of an added control line.
    Type: Application
    Filed: December 29, 2000
    Publication date: July 4, 2002
    Inventors: Keith Self, John Urbanski
  • Controller that supports data merging utilizing a slice addressable memory array
    Patent number: 6134632
    Abstract: A computer system including a slice-addressable multi-port memory array is disclosed. The slice-addressable multi-port memory array provides a mechanism for efficient data merging in a memory controller in accordance with an associated array of slice-enable bits. Each slice of the memory array is individually designated by a slice-enable bit, and only those slices of a word line enabled for writing that are designated by a slice-enable bit are modified during a write operation. In a subsequent write-merge operation, the slices of the word line enabled for writing that were not designated by slice-enable bits during the write operation are modified, and the slices that were modified during the preceding write operation are unaffected, thereby providing for efficient merger of data from the write operation and data from the write-merge operation in a single word line.
    Type: Grant
    Filed: January 26, 1998
    Date of Patent: October 17, 2000
    Assignee: Intel Corporation
    Inventors: Lily Pao Looi, Sin Tan, John Urbanski, Christopher Van Beek