Abstract: A method and computer program product for determining an internal temperature of a computing device, a power consumption factor for the computing device, and an airflow factor for the computing device. An approximated ambient air temperature is generated based upon the internal temperature, power consumption factor, and the airflow factor. A workload factor is determined for the computing device and a fan speed for the computing device is controlled based at least in part upon the approximated ambient air temperature and the workload factor.

Abstract: A system having: a midplane having air flow channels therein; a disk drive mounted to a first side of the midplane; and a temperature sensors mounted to the midplane. The system includes a pair of electrical chassis connected to a second side of the midplane. A first one of the chassis has therein: a fan; and a fan controller for controlling speed of the fan in response to a temperature control signal. A second one of the chassis has therein: a microprocessor for: detecting temperature signals produced by the temperature sensors; comparing differences between the detected temperature signals; and selecting one of the detected temperature control signal from the compared differences as the temperature control signal. A faulty one of the temperature sensors is detected by: selecting one of the detected temperature control signal as the faulty one of the plurality of temperature sensors from the compared differences.

Abstract: A system having: a midplane having air flow channels therein; a disk drive mounted to a first side of the midplane; and a temperature sensors mounted to the midplane. The system includes a pair of electrical chassis connected to a second side of the midplane. A first one of the chassis has therein: a fan; and a fan controller for controlling speed of the fan in response to a temperature control signal. A second one of the chassis has therein: a microprocessor for: detecting temperature signals produced by the temperature sensors; comparing differences between the detected temperature signals; and selecting one of the detected temperature control signal from the compared differences as the temperature control signal. A faulty one of the temperature sensors is detected by: selecting one of the detected temperature control signal as the faulty one of the plurality of temperature sensors from the compared differences.

Abstract: A system having: a midplane having air flow channels therein; a disk drive mounted to a first side of the midplane; and a temperature sensors mounted to the midplane. The system includes a pair of electrical chassis connected to a second side of the midplane. A first one of the chassis has therein: a fan; and a fan controller for controlling speed of the fan in response to a temperature control signal. A second one of the chassis has therein: a microprocessor for: detecting temperature signals produced by the temperature sensors; comparing differences between the detected temperature signals; and selecting one of the detected temperature control signal from the compared differences as the temperature control signal. A faulty one of the temperature sensors is detected by: selecting one of the detected temperature control signal as the faulty one of the plurality of temperature sensors from the compared differences.

Abstract: A data storage system includes a first storage processor for storing and retrieving data from a data storage array for at least one host computer; a second storage processor, coupled to the first storage processor by a communication link, for storing and retrieving data from the data storage array for the at least one host computer; a number M of multiplexers, M being greater than one, each of the multiplexers being coupled to the first storage processor and the second storage processor for receiving data signals from the first storage processor and the second storage processor and transmitting the data signals to a disk drive device; a number A of arbiters, each being coupled to the first storage processor, the second storage processor and a number N of the plurality of multiplexers, for receiving arbiter control signals from the first storage processor and the second storage processor and transmitting multiplexer control signals to each of the number N of the plurality of multiplexers; and a midplane device

Abstract: A data storage system has a chassis and a pair of printed circuit boards disposed in the chassis. Each one of the pair of printed circuit boards has disposed thereon a processor, a translator controlled by the processor, a SAS expander having a bidirectional front end port and multiple bidirectional backend ports, and an expansion port, and a SAS controller coupled between the translator and the expander. The system also has an interposer printed circuit board disposed in the chassis, and multiple multiplexers disposed on the interposer printed circuit board. Each one of the multiplexers has a pair of bidirectional front end ports and a pair of bidirectional back end ports. A first one of the pair of bidirectional front end ports is connected to a corresponding backend port of the SAS expander disposed on a first one of the pair of storage processor printed circuit boards.

Abstract: A data storage system has a circuit board module, a set of Serial ATA devices, and a set of Serial ATA cables connecting the circuit board module to the set of Serial ATA devices. The circuit board module includes a circuit board, multiple host circuits mounted to the circuit board and multiplexer circuitry mounted to the circuit board. Each host circuit is configured to perform data storage operations on the behalf of an external client. The multiplexer circuitry is configured to (i) receive control signals from the host circuits and (ii) provide communications pathways between the host circuits and the set of Serial ATA devices in response to the control signals. Such an embodiment alleviates the need for multiple versions of disk drive assemblies and their associated costs.

Abstract: A data storage system having a first chassis, such first chassis having a pair of SAS expanders and a second chassis having a pair of SAS expanders. The first one of the pair of SAS expanders is connected to only an expansion port of a first one of a pair of signal processor printed circuit boards in the first one of the chassis. An expansion port of a second one of the pair of SAS expander is connected to only the expansion port of a second one of the pair of signal processor printed circuit boards in the second one of the chassis.

Abstract: A data storage system includes a disk drive array including a plurality of disk drives; a first storage processor for controlling the operation of the data storage system; a second storage processor for controlling the operation of the data storage system; a first arbiter for controlling communication of data from the first storage processor and the second storage processor to a first group of disk drives of the disk drive array; and a second arbiter for controlling communication of data from the first storage processor and the second storage processor to a second group of disk drives of the disk drive array. Selected data is redundantly stored on disk drives in the first group of disk drives and the second group of disk drives, such that, upon failure of the first arbiter, the selected data is available to the first storage processor and the second storage processor through the second arbiter.

Abstract: An improved data storage system has a set of storage devices, a first storage processor and a second storage processor for storing data into and retrieving data from the set of storage devices. The first storage processor includes a processing circuit and a packaged IC device which has a first set of ports and a second set of ports. The processing circuit is adapted to configure the packaged IC device to provide (i) communications to the set of storage devices through the first set of ports and (ii) other communications to the second storage processor through the second set of ports. The processing circuit is further adapted to pass communications between the first storage processor and the set of storage devices through the first set of ports; and pass communications between the first storage processor and the second storage processor through the second set of ports.

Abstract: Disk drive spin-up is staggered to reduce peak power requirements. Spin-up of the drives is controlled by selectively delaying voltage inputs to the disk drives. Alternately, spin-up of the drives is controlled by staggering the timing of communications to the disk drives.

Abstract: Data storage equipment includes a first storage processor comprising a processing circuit and a collection of packaged integrated circuit devices which has a first set of ports and a second set of ports; a second storage processor; and an interconnect coupled between the first and second storage processors. The processing circuit of the first storage processor is adapted to execute as follows. The collection of packaged integrated circuit devices of the first storage processor is configured to provide (i) communications to a set of storage devices through the first set of ports of the collection of packaged integrated circuit devices and (ii) other communications to the second storage processor through the second set of ports of the collection of packaged integrated circuit devices. Communications is passed between the first storage processor and the set of storage devices through the first set of ports of the collection of packaged integrated circuit devices.

Abstract: A data storage system has a chassis and a pair of printed circuit boards disposed in the chassis. Each one of the pair of printed circuit boards has disposed thereon a processor, a translator controlled by the processor, a SAS expander having a bidirectional front end port and multiple bidirectional backend ports, and an expansion port, and a SAS controller coupled between the translator and the expander. The system also has an interposer printed circuit board disposed in the chassis, and multiple multiplexers disposed on the interposer printed circuit board. Each one of the multiplexers has a pair of bidirectional front end ports and a pair of bidirectional back end ports. A first one of the pair of bidirectional front end ports is connected to a corresponding backend port of the SAS expander disposed on a first one of the pair of storage processor printed circuit boards.

Abstract: Disk drive spin-up is staggered to reduce peak power requirements. Spin-up of the drives is controlled by selectively delaying voltage inputs to the disk drives. Alternately, spin-up of the drives is controlled by staggering the timing of communications to the disk drives.

Abstract: A data storage system has a first storage processor, a second storage processor, and a communications subsystem. The communications subsystem has (i) an interfacing portion interconnected between the first storage processor and the second storage processor, (ii) a clock circuit coupled to the interfacing portion, and (iii) a controller coupled to the interfacing portion and the clock circuit. The controller is configured to enable operation of the interfacing portion to provide communications between the first and second storage processors, sense a failure within the clock circuit, and reset the interfacing portion in response to the sensed failure to enable one of the first and second storage processors to continue operation. Such resetting of the interfacing portion prevents the remaining storage processor from locking up, thus freeing that storage processor so that it is capable of continuing to operate even after the failure.

Abstract: Modules coupled to multiple connectors can check to see if full connectivity is provided through the connectors. If it is not, for instance because the connectors are mis-seated, the modules can prevent themselves from fully powering up. In a storage environment, a first module is coupled to connectors. The connectors are coupled to corresponding disk drives. Each connector provides a connectivity indication. The module prevents itself from fully powering up if it fails to receive a connectivity indication from a subset of connectors coupled to boot disks.

Abstract: Described is a midplane-less data storage enclosure having a control board module with an electrical connector and a bulkhead assembly with a plurality of spaced-apart disk-drive guides coupled to a bulkhead. The disk-drive guides and bulkhead together define a plurality of disk-drive slots. The bulkhead has connected thereto a plurality of first electrical connectors and a second electrical connector in electrical communication with each of the first electrical connectors. Each slot slidably receives a storage disk drive such that the storage disk drive electrically connects to one of the first electrical connectors. The second electrical connector is electrically connected to the connector of the control board module so that each storage disk drive connected to one of the first electrical connectors is in electrical communication with the control board module.

Abstract: A system has a Serial ATA device and a subsystem. The subsystem includes multiple hosts, and a communications medium which interconnects the hosts to the device. The hosts are configured to share control of the device through the communications medium. First and second hosts, when transitioning control of the device, are configured to (i) send a sleep command from the first host to the device, the sleep command directing the device to transition from a normal operating mode to a sleep mode, (ii) provide a notification signal from the first host to the second host, the notification signal indicating that the first host has released control of the device to the second host, and (iii) send a wake command from the second host to the device in response to the notification signal, the wake command directing the device to transition from the sleep mode to the normal operating mode.

Abstract: A Serial ATA communications system has a host, a device, and a Serial ATA communications cable that connects the host to the device. The Serial ATA communications cable includes (i) a pair of transmit lines configured to carry a differential mode transmit signal, (ii) a pair of receive lines configured to carry a differential mode receive signal, and (iii) a set of ground lines. The host includes a transmit circuit configured to connect to the pair of transmit lines of the Serial ATA communications cable, a receive circuit configured to connect to the pair of receive lines of the Serial ATA communications cable, and a sensor. The sensor is configured to provide an output signal indicating whether a Serial ATA device is connected to the Serial ATA communications cable in response to a test signal applied to the set of ground lines.