Patents by Inventor John V. Jensen

John V. Jensen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9072366
    Abstract: A utility bucket backpack apparatus having an upper strap and a lower strap may have each of the upper and lower straps connected to two backpack straps. The lower strap may further be connected to a bottom strap. The upper strap may further be connected to two handle straps. The upper strap and the lower strap may also be removably connected to the outer circumference of a utility bucket.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: July 7, 2015
    Inventors: John V. Jensen, Michael C. Gibbon
  • Publication number: 20150076202
    Abstract: A utility bucket backpack apparatus having an upper strap and a lower strap may have each of the upper and lower straps connected to two backpack straps. The lower strap may further be connected to a bottom strap. The upper strap may further be connected to two handle straps. The upper strap and the lower strap may also be removably connected to the outer circumference of a utility bucket.
    Type: Application
    Filed: September 17, 2013
    Publication date: March 19, 2015
    Inventors: John V. Jensen, Michael C. Gibbon
  • Patent number: 7325222
    Abstract: A method for verifying reticle enhancement technique latent image sensitivity to mask manufacturing errors. The method includes the steps of revising a polygon based on mask CD distributions to provide a virtual mask, imaging the virtual mask to obtain response function statistical parameters, and comparing the statistical parameters to process tolerance requirements. Preferably, the method includes the steps of simulating an aerial and/or latent image of the virtual mask, calculating response functions based on the mask image simulation, collecting measurements and calculating statistical parameters based on the response functions, and comparing the statistical parameters with design rule requirements (i.e., for DI yield percentage for required mask manufacturing specification). The virtual mask is obtained by using mask CD distribution to induce statistical variations to layouts which have passed through the conventional OPC procedure.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: January 29, 2008
    Assignee: LSI Logic Corporation
    Inventors: Nadya G. Strelkova, Ebo H. Croffie, John V. Jensen
  • Patent number: 7005217
    Abstract: A photolithographic mask for receiving light at a wavelength, phase, and intensity and printing a desired image on a substrate with an optical system. The mask is formed on an optically transmissive substrate, called a mask blank. The mask blank is preferably one hundred percent transmissive of the light intensity at the wavelength. At least one layer of an attenuated material that is at least partially transmissive to the wavelength of the light is formed on the optically transmissive substrate. The at least one layer of the attenuated material preferably blocks from about fifty percent to about ninety-four percent of the intensity of the light at the wavelength, whereas the prior art masks use materials that block about six percent of the intensity of the light at the wavelength. The attenuated material defines three feature types on the mask, including a primary image having edges, a scattering bar disposed near the edges of the primary image, and a background region.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: February 28, 2006
    Assignee: LSI Logic Corporation
    Inventors: George E. Bailey, Neal P. Callan, John V. Jensen
  • Publication number: 20040197674
    Abstract: A photolithographic mask for receiving light at a wavelength, phase, and intensity and printing a desired image on a substrate with an optical system. The mask is formed on an optically transmissive substrate, called a mask blank. The mask blank is preferably one hundred percent transmissive of the light intensity at the wavelength. At least one layer of an attenuated material that is at least partially transmissive to the wavelength of the light is formed on the optically transmissive substrate. The at least one layer of the attenuated material preferably blocks from about fifty percent to about ninety-four percent of the intensity of the light at the wavelength, whereas the prior art masks use materials that block about six percent of the intensity of the light at the wavelength. The attenuated material defines three feature types on the mask, including a primary image having edges, a scattering bar disposed near the edges of the primary image, and a background region.
    Type: Application
    Filed: April 4, 2003
    Publication date: October 7, 2004
    Inventors: George E. Bailey, Neal P. Callan, John V. Jensen
  • Patent number: 6532585
    Abstract: The present invention is a method and apparatus for applying one-dimensional proximity correction to a piece of a mask pattern, by segmenting a first piece of a mask pattern with horizontal dividing lines into a plurality of segments, segmenting a second piece of said mask pattern with said horizontal dividing lines into a second plurality of segments, and applying proximity correction to a first segment from said first plurality of segments taking into consideration a second segment from said second plurality of segments.
    Type: Grant
    Filed: November 14, 2000
    Date of Patent: March 11, 2003
    Assignee: LSI Logic Corporation
    Inventors: Dusan Petranovic, Ranko Scepanovic, Edwin Jones, Richard Schinella, Nicholas F. Pasch, Mario Garza, Keith K. Chao, John V. Jensen, Nicholas K. Eib
  • Patent number: 6499003
    Abstract: The present invention is a method and apparatus for applying proximity correction to a piece of a mask pattern, by segmenting the piece into a plurality of segments, and applying proximity correction to a first segment without taking into consideration the other segments of the piece.
    Type: Grant
    Filed: March 3, 1998
    Date of Patent: December 24, 2002
    Assignee: LSI Logic Corporation
    Inventors: Edwin Jones, Dusan Petranovic, Ranko Scepanovic, Richard Schinella, Nicholas F. Pasch, Mario Garza, Keith K. Chao, John V. Jensen, Nicholas K. Eib
  • Publication number: 20020004714
    Abstract: The present invention is a method and apparatus for applying proximity correction to a piece of a mask pattern, by segmenting the piece into a plurality of segments, and applying proximity correction to a first segment without taking into consideration the other segments of the piece.
    Type: Application
    Filed: March 3, 1998
    Publication date: January 10, 2002
    Inventors: EDWIN JONES, DUSAN PETRANOVIC, RANKO SCEPANOVIC, RICHARD SCHINELLA, NICHOLAS F. PASCH, MARIO GARZA, KEITH K. CHAO, JOHN V. JENSEN, NICHOLAS K. EIB
  • Patent number: 6282696
    Abstract: A method is disclosed for identifying regions of an integrated circuit layout design where optical proximity correction will be most useful and then performing optical proximity correction on those regions only. More specifically, the method includes the following steps: (a) analyzing an integrated circuit layout design with a design rule checker to locate features of the integrated circuit layout design meeting predefined criteria; and (b) performing optical proximity correction on the features meeting the criteria in order to generate a reticle design. The criteria employed by the design rule checker to select features include outside corners on patterns, inside corners on features, feature size, feature shape, and feature angles.
    Type: Grant
    Filed: March 9, 1999
    Date of Patent: August 28, 2001
    Assignee: LSI Logic Corporation
    Inventors: Mario Garza, Nicholas K. Eib, John V. Jensen, Keith K. Chao
  • Patent number: 6269472
    Abstract: Disclosed is a method for correcting a layout design using a design rule checker. The method includes providing a layout design file having the layout design that is to be corrected for optical proximity by the design rule checker. Providing a run set to the design rule checker. The run set includes a plurality of correction values that are used to correct a plurality of features of the layout design that have a selected space dimension. Identifying each of the plurality of features that have the selected space dimension. The method further includes correcting each of the plurality of features that have the selected space dimension with one correction value of the plurality of correction values of the run set. Preferably, the run set is generated from a correction table that has the plurality of correction values.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: July 31, 2001
    Assignee: LSI Logic Corporation
    Inventors: Mario Garza, John V. Jensen, Nicholas K. Eib, Keith K. Chao
  • Patent number: 6175953
    Abstract: The present invention is a method and apparatus for systematically applying proximity corrections to a mask pattern, wherein the pattern is divided into a grid of equally sized grid rectangles, an inner rectangle comprising a plurality of grid rectangles is formed, an outer rectangle comprising a second plurality of grid rectangles and the inner rectangle is formed and proximity correction is applied to the pattern contained within the inner rectangle as a function of the pattern contained within the outer rectangle.
    Type: Grant
    Filed: March 3, 1998
    Date of Patent: January 16, 2001
    Assignee: LSI Logic Corporation
    Inventors: Ranko Scepanovic, Dusan Petranovic, Edwin Jones, Richard Schinella, Nicholas F. Pasch, Mario Garza, Keith K. Chao, John V. Jensen, Nicholas K. Eib
  • Patent number: 6174630
    Abstract: The present invention is a method and apparatus for applying one-dimensional proximity correction to a piece of a mask pattern, by segmenting a first piece of a mask pattern with horizontal dividing lines into a plurality of segments, segmenting a second piece of said mask pattern with said horizontal dividing lines into a second plurality of segments, and applying proximity correction to a first segment from said first plurality of segments taking into consideration a second segment from said second plurality of segments.
    Type: Grant
    Filed: March 3, 1998
    Date of Patent: January 16, 2001
    Assignee: LSI Logic Corporation
    Inventors: Dusan Petranovic, Ranko Scepanovic, Edwin Jones, Richard Schinella, Nicholas F. Pasch, Mario Garza, Keith K. Chao, John V. Jensen, Nicholas K. Eib
  • Patent number: 5900338
    Abstract: A method is disclosed for identifying regions of an integrated circuit layout design where optical proximity correction will be most useful and then performing optical proximity correction on those regions only. More specifically, the method includes the following steps: (a) analyzing an integrated circuit layout design with a design rule checker to locate features of the integrated circuit layout design meeting predefined criteria; and (b) performing optical proximity correction on the features meeting the criteria in order to generate a reticle design. The criteria employed by the design rule checker to select features include outside corners on patterns, inside corners on features, feature size, feature shape, and feature angles.
    Type: Grant
    Filed: August 15, 1997
    Date of Patent: May 4, 1999
    Assignee: LSI Logic Corporation
    Inventors: Mario Garza, Nicholas K. Eib, John V. Jensen, Keith K. Chao
  • Patent number: 5705301
    Abstract: A method is disclosed for identifying regions of an integrated circuit layout design where optical proximity correction will be most useful and then performing optical proximity correction on those regions only. More specifically, the method includes the following steps: (a) analyzing an integrated circuit layout design with a design role checker to locate features of the integrated circuit layout design meeting predefined criteria; and (b) performing optical proximity correction on the features meeting the criteria in order to generate a reticle design. The criteria employed by the design role checker to select features include outside corners on patterns, inside corners on features, feature size, feature shape, and feature angles.
    Type: Grant
    Filed: February 27, 1996
    Date of Patent: January 6, 1998
    Assignee: LSI Logic Corporation
    Inventors: Mario Garza, Nicholas K. Eib, John V. Jensen, Keith K. Chao
  • Patent number: 5703376
    Abstract: A system for lithographic rastering of an image, defined by an array of pixels, onto an image-accepting substrate that allows irradiation of the total pixel pattern in reduced time. The total image is first divided into a collection of one or more geometrically isolated pixel arrays, with all pixels in an array being connected to each other. Each pixel array is decomposed into a fine region, consisting of all image pixels within P pixels of a boundary of that array, where P is a selected positive integer, such as 1, 2 or 3, and a bulk region consisting of all image pixels in that array that are not part of a fine region. A pixel array may include one or more bulk regions and one or more fine regions. A fine region for a pixel array is further decomposed into a first fine sub-region with pixel width at least equal to P1 pixels, where P1 is a selected integer satisfying 2.ltoreq.P1.ltoreq.P, and a second fine sub-region with pixel width no greater than P1-1 pixels.
    Type: Grant
    Filed: June 5, 1996
    Date of Patent: December 30, 1997
    Assignee: LSI Logic Corporation
    Inventor: John V. Jensen