Abstract: Memory channel training parameters are function of electrical characteristics of memory devices, processor(s) and memory channel(s). Training steps can be skipped if the BIOS can determine that the memory devices, motherboard and processor have not changed since the last boot. Memory devices contain a serial number for tracking purposes and most motherboards contain a serial number. Many processors do not provide a mechanism by which the BIOS can track the processor. Described herein are techniques that allow the BIOS to track a processor and detect a swap without violating privacy/security requirements.

Abstract: Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.

Abstract: In an embodiment, the effect of signal phase difference on a memory system is tested for various operating states. The various operating states may be represented as respective sample points on a plane defined by a range of values for a difference in signal phases and a range of values for another operating state parameter. In various embodiments, sample points for a round of crosstalk testing may include two sample points which are offset from the same reference point on the plane along different respective axes, where the axes are oblique to one another.

Abstract: A method includes determining an amount of memory space in a memory device available for memory mirroring. The method further includes presenting the available memory space to an operating system. The method further includes selecting at least a portion of the amount of memory space to be used for memory mirroring with the operating system. The method further includes adding a non-selected portion of the available memory to memory space available to the operating system during operation. An associated system and machine readable medium are also disclosed.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for the active training of memory command timing. In some embodiments, the CMD/CTL timing is actively trained using active feedback between memory modules and the memory controller. Other embodiments are described and claimed.

Abstract: A modular BIOS update mechanism provides a standardized method to update options ROMs and to provide video and processor microcode upgrades in a computer system without requiring a complete replacement of the system BIOS. The MBU mechanism provides several advantages. First, new features and BIOS bugs from earlier release may be delivered to an installed base of end-user systems even if direct OEM support cannot be identified. Also, BIOS components may be provided as a validated set of revisions. With resort to a validation matrix, BIOS updates may be managed easily. The modular BIOS update is particularly useful in systems having several independent BIOS's stored within unitary firmware.

Abstract: A method includes determining an amount of memory space in a memory device available for memory mirroring. The method further includes presenting the available memory space to an operating system. The method further includes selecting at least a portion of the amount of memory space to be used for memory mirroring with the operating system. The method further includes adding a non-selected portion of the available memory to memory space available to the operating system during operation. An associated system and machine readable medium are also disclosed.

Abstract: A secure method for updating computer firmware online is described. The firmware storage locations are write protected prior to loading the operating system. Updating the firmware after loading the operating system helps to reduce downtime.

Abstract: A modular BIOS update mechanism provides a standardized method to update options ROMs and to provide video and processor microcode upgrades in a computer system without requiring a complete replacement of the system BIOS. The MBU mechanism provides several advantages. First, new features and BIOS bugs from earlier release may be delivered to an installed base of end-user systems even if direct OEM support cannot be identified. Also, BIOS components may be provided as a validated set of revisions. With resort to a validation matrix, BIOS updates may be managed easily. The modular BIOS update is particularly useful in systems having several independent BIOS's stored within unitary firmware.

Abstract: In one embodiment of the present invention, a method includes storing system management mode data in a cache of a system during a system management mode; and preventing the system from leaving the system management mode until the system management mode data is evicted from the cache.

Abstract: One embodiment of the invention provides a firmware architecture which splits firmware modules to support safe updates of specific modules as well as supporting multiple different processors. A firmware image is partitioned into several different binaries based on their update requirements and processor/platform dependence. A firmware interface table enables safe updates by enabling the option of redundant copies of specific modules as well as supporting systems with different and/or multiple processor types, mixed processors from the same family, and/or fault resilient firmware updates.

Abstract: In one embodiment of the present invention, a method includes storing system management mode data in a cache of a system during a system management mode; and preventing the system from leaving the system management mode until the system management mode data is evicted from the cache.

Abstract: One embodiment of the invention provides a firmware architecture which splits firmware modules to support safe updates of specific modules as well as supporting multiple different processors. A firmware image is partitioned into several different binaries based on their update requirements and processor/platform dependence. A firmware interface table enables safe updates by enabling the option of redundant copies of specific modules as well as supporting systems with different and/or multiple processor types, mixed processors from the same family, and/or fault resilient firmware updates.

Abstract: A secure method for updating computer firmware online is described. The firmware storage locations are write protected prior to loading the operating system. Updating the firmware after loading the operating system helps to reduce downtime.

Abstract: A startup program for protecting against corruption of firmware resides in multiple blocks of a firmware device in a processor-based system. While the firmware device typically stores code, the device may additionally store data that is accessible to application programs. The startup program confirms that the block from which it executes is a valid startup block. If the block is not a valid startup block, the startup program searches the other blocks in the firmware device for a valid startup block. Upon identifying a valid startup block, the startup program sets an execution address such that subsequent initialization of the processor-based system occurs from the startup block.

Abstract: A method and apparatus for initializing a computer system, which includes a lockable nonvolatile memory coupled to a processor having maskable address lines and a cache, when a nonvolatile memory update is in process. When an update is in process, the nonvolatile memory is unlocked in response to the initialization event only if address line masking is disabled, and at least a portion of the processor cache is invalidated to ensure the processor will fetch the first instruction from the nonvolatile memory.

Abstract: A startup program for protecting against corruption of firmware resides in multiple blocks of a firmware device in a processor-based system. While the firmware device typically stores code, the device may additionally store data that is accessible to application programs. The startup program confirms that the block from which it executes is a valid startup block. If the block is not a valid startup block, the startup program searches the other blocks in the firmware device for a valid startup block. Upon identifying a valid startup block, the startup program sets an execution address such that subsequent initialization of the processor-based system occurs from the startup block.

Abstract: A system and method for upgrading a boot block of a firmware program is disclosed. A copy of a replacement boot block is transferred to a firmware device, and then the execution address is changed to point to this new location. The replacement boot block is then copied over the original boot block. Once the copying is complete, the execution address is restored to the original location in the firmware program.

Abstract: A method and apparatus for booting an operating system having at least one boot component comprising the steps of accessing an ordered list identifying the at least one boot component; accessing each of the at least one boot component using the ordered list; computing a first hash value from the at least one boot component; accessing a second hash value, the second hash value being secure; comparing the first hash value to the second hash value; and booting the operating system if the first hash value matches the second hash value.