Patents by Inventor John V. Spohnheimer

John V. Spohnheimer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10134890
    Abstract: A vertical power switching device, such as a vertical superjunction metal-oxide-semiconductor field-effect-transistor (MOSFET), in which termination structures in the corners of the integrated circuit are stretched to efficiently shape the lateral electric field. Termination structures in the device include such features as doped regions, field plates, insulator films, and high-voltage conductive regions and elements at the applied substrate voltage. Edges of these termination structures are shaped and placed according to a 2nd-order smooth, non-circular analytic function so as to extend deeper into the die corner from the core region of the device than a constant-distance path. Also disclosed are electrically floating guard rings in the termination region, to inhibit triggering of parasitic p-n-p-n structures.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: November 20, 2018
    Assignee: D3 Semiconductor LLC
    Inventors: Thomas E. Harrington, III, John V. Spohnheimer, Zhijun Qu
  • Publication number: 20180277673
    Abstract: A vertical power switching device, such as a vertical superjunction metal-oxide-semiconductor field-effect-transistor (MOSFET), in which termination structures in the corners of the integrated circuit are stretched to efficiently shape the lateral electric field. Termination structures in the device include such features as doped regions, field plates, insulator films, and high-voltage conductive regions and elements at the applied substrate voltage. Edges of these termination structures are shaped and placed according to a 2nd-order smooth, non-circular analytic function so as to extend deeper into the die corner from the core region of the device than a constant-distance path. Also disclosed are electrically floating guard rings in the termination region, to inhibit triggering of parasitic p-n-p-n structures.
    Type: Application
    Filed: October 17, 2017
    Publication date: September 27, 2018
    Inventors: Thomas E. Harrington, III, John V. Spohnheimer, Zhijun Qu
  • Patent number: 9806186
    Abstract: A vertical power switching device, such as a vertical superjunction metal-oxide-semiconductor field-effect-transistor (MOSFET), in which termination structures in the corners of the integrated circuit are stretched to efficiently shape the lateral electric field. Termination structures in the device include such features as doped regions, field plates, insulator films, and high-voltage conductive regions and elements at the applied substrate voltage. Edges of these termination structures are shaped and placed according to a 2nd-order smooth, non-circular analytic function so as to extend deeper into the die corner from the core region of the device than a constant-distance path. Also disclosed are electrically floating guard rings in the termination region, to inhibit triggering of parasitic p-n-p-n structures.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: October 31, 2017
    Assignee: D3 Semiconductor LLC
    Inventors: Thomas E. Harrington, III, John V. Spohnheimer, Zhijun Qu
  • Publication number: 20170098705
    Abstract: A vertical power switching device, such as a vertical superjunction metal-oxide-semiconductor field-effect-transistor (MOSFET), in which termination structures in the corners of the integrated circuit are stretched to efficiently shape the lateral electric field. Termination structures in the device include such features as doped regions, field plates, insulator films, and high-voltage conductive regions and elements at the applied substrate voltage. Edges of these termination structures are shaped and placed according to a 2nd-order smooth, non-circular analytic function so as to extend deeper into the die corner from the core region of the device than a constant-distance path. Also disclosed are electrically floating guard rings in the termination region, to inhibit triggering of parasitic p-n-p-n structures.
    Type: Application
    Filed: October 2, 2015
    Publication date: April 6, 2017
    Inventors: Thomas E. Harrington, III, John V. Spohnheimer, Zhijun Qu
  • Patent number: 4406949
    Abstract: A method and apparatus are disclosed for aligning an integrated circuit die (110) by use of a machine which directs a laser beam (32) downward on a wafer containing the die (110). Each die (110) is provided with one or more targets (52, 64, 78). A target (52) comprises an N+ region (56) within the target (52) and a layer of polysilicon (56) over an oxide layer (70). A laser beam (32) is scanned across the target (52) to detect a transition across an edge of a polysilicon layer (68). The transition is detected by the generation of charge carriers (36) within the region (34). The region (34) has an opposite conductivity type from that of the substrate (10) thus forming a PN junction. The PN junction is reversed biased by a voltage source (38) which is connected in series with a resistor (40) between the substrate (10) and the region (34). A center point is determined by calculating the midpoint between transitions. The establishment of a center of the target (52) establishes a reference point.
    Type: Grant
    Filed: July 13, 1981
    Date of Patent: September 27, 1983
    Assignee: Mostek Corporation
    Inventor: John V. Spohnheimer
  • Patent number: 4358659
    Abstract: A laser beam (38) is focused on the surface of a semiconductor substrate (10) by translating an objective lens (70) along the path of the laser beam (38). The substrate (10) is fabricated to have a region (12) of an opposite conductivity type and to have a barrier layer (18) to the laser beam (38). An opening (16) is provided in the barrier layer (18) to permit the laser beam (38) to strike the substrate (10). A voltage source (24) and resistance (26) are connected in series between the substrate (10) and the region (12) to form a reverse biased diode junction. When the laser beam (38) strikes the substrate (10) charge carriers (42) are generated to produce a current through the resistor (26). The current flow through the circuit is measured by a control circuit (84) which drives a mechanism (72, 74, 76, 78, 80) to position the objective lens (70) such that the focus point of the laser beam (38) is positioned at the surface of the substrate (10).
    Type: Grant
    Filed: July 13, 1981
    Date of Patent: November 9, 1982
    Assignee: Mostek Corporation
    Inventor: John V. Spohnheimer