Patents by Inventor John Vesce

John Vesce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11277909
    Abstract: The disclosure provides a three-dimensional circuit assembly including a printed circuit board comprising a top film surface and a bottom film surface opposite to the top film surface. The three-dimensional circuit assembly may also include a first layer of a composite material bonded or laminated on the top film surface. The three-dimensional circuit assembly may further include a second layer of the composite material bonded or laminated on the bottom film surface of the printed circuit board.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: March 15, 2022
    Assignee: TTM TECHNOLOGIES INC.
    Inventors: John Vesce, III, Joseph William Heery, Jr.
  • Publication number: 20210068250
    Abstract: The disclosure provides a three-dimensional circuit assembly including a printed circuit board comprising a top film surface and a bottom film surface opposite to the top film surface. The three-dimensional circuit assembly may also include a first layer of a composite material bonded or laminated on the top film surface. The three-dimensional circuit assembly may further include a second layer of the composite material bonded or laminated on the bottom film surface of the printed circuit board.
    Type: Application
    Filed: August 28, 2020
    Publication date: March 4, 2021
    Inventors: John Vesce, III, Joseph William Heery, JR.
  • Patent number: 9532465
    Abstract: The invention provides a method of fabricating an interconnect comprising aligning and stacking a plurality of printed circuit boards with at least one adhesive component, laminating the printed circuit boards and the adhesive component, preparing bonded pair holes, depositing a copper seed layer, forming a copper plate image, electroplating a copper layer, removing a plate resist and depositing an insulator layer.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: December 27, 2016
    Inventors: John Vesce, Joseph William Heery, Jr.
  • Publication number: 20130269183
    Abstract: Some embodiments of the invention provide a method of fabricating an interconnect comprising aligning and stacking a plurality of printed circuit boards with at least one adhesive component, laminating the printed circuit boards and the adhesive component, preparing bonded pair holes, depositing a copper seed layer, forming a copper plate image, electroplating a copper layer, removing a plate resist and depositing an insulator layer.
    Type: Application
    Filed: March 28, 2013
    Publication date: October 17, 2013
    Inventors: John Vesce, Joseph William Heery, JR.