Patents by Inventor John Vranich

John Vranich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for testing mathematical algorithms
    Patent number: 7730356
    Abstract: A method and apparatus for testing mathematical programs where code coverage is exceedingly difficult to hit with random data test vectors (probability <2?64) is provided. To enable testing of the mathematical program, instructions in the mathematical program are trapped. Errors are injected through the use of any status/control flag where an error can be created and be rectified later by a reversible operation so that the result of the mathematical operation is not modified by the injected error.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: June 1, 2010
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, John Vranich, Pierre Laurent, Daniel Cutter, Wajdi K. Feghali, Andrew Milne, Erdinc Ozturk
  • High performance raid-6 system architecture with pattern matching
    Patent number: 7664915
    Abstract: An acceleration unit offloads computationally intensive tasks from a processor. The acceleration unit includes two data processing paths each having an Arithmetic Logical Unit and sharing a single multiplier unit. Each data processing path may perform configurable operations in parallel on a same data. Special multiplexer paths and instructions are provided to allow P and Q type syndromes to be computed on a stripe in a single-pass of the data through the acceleration unit.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: February 16, 2010
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, Gilbert Wolrich, Kirk S. Yap, Wajdi K. Feghali, John Vranich, Robert P. Ottavi
  • METHOD AND APPARATUS FOR TESTING MATHEMATICAL ALGORITHMS
    Publication number: 20090089617
    Abstract: A method and apparatus for testing mathematical programs where code coverage is exceedingly difficult to hit with random data test vectors (probability <2?64) is provided. To enable testing of the mathematical program, instructions in the mathematical program are trapped. Errors are injected through the use of any status/control flag where an error can be created and be rectified later by a reversible operation so that the result of the mathematical operation is not modified by the injected error.
    Type: Application
    Filed: September 28, 2007
    Publication date: April 2, 2009
    Inventors: Vinodh Gopal, John Vranich, Pierre Laurent, Daniel Cutter, Wajdi K. Feghali, Andrew Milne, Erdinc Ozturk
  • High performance raid-6 system architecture with pattern matching
    Publication number: 20080148025
    Abstract: An acceleration unit offloads computationally intensive tasks from a processor. The acceleration unit includes two data processing paths each having an Arithmetic Logical Unit and sharing a single multiplier unit. Each data processing path may perform configurable operations in parallel on a same data. Special multiplexer paths and instructions are provided to allow P and Q type syndromes to be computed on a stripe in a single-pass of the data through the acceleration unit.
    Type: Application
    Filed: December 19, 2006
    Publication date: June 19, 2008
    Inventors: Vinodh Gopal, Gilbert Wolrich, Kirk S. Yap, Wajdi K. Feghali, John Vranich, Robert P. Ottavi