Patents by Inventor John W. Andberg

John W. Andberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10297339
    Abstract: Example features or aspects of the present invention are described in relation to a small, quiet integrated cooling system for an apparatus for testing electronic devices. Characteristics of the test apparatus including a low noise output, low power consumption and a compact size with a small spatial and volume footprint are selected for deployment and use in a an office like environment. The test apparatus comprises a chassis frame and a cooler frame disposed within the chassis frame and thus integrated within the test apparatus, which has a reduced form factor suitable for the in-office deployment. Embodiments offer the ability to maintain the working fluid at a constant temperature.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: May 21, 2019
    Assignee: Advantest Corporation
    Inventors: Brent Thordarson, John W. Andberg, Koei Nishiura
  • Patent number: 9335347
    Abstract: Disclosed herein is a cost effective, efficient, massively parallel multi-wafer test cell. Additionally, this test cell can be used for both single-touchdown and multiple-touchdown applications. The invention uses a novel “split-cartridge” design, combined with a method for aligning wafers when they are separated from the probe card assembly, to create a cost effective, efficient multi-wafer test cell. A “probe-card stops” design may be used within the cartridge to simplify the overall cartridge design and operation.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: May 10, 2016
    Assignee: ADVANTEST CORPORATION
    Inventors: John W. Andberg, Ira H. Leventhal, Matthew W. Losey, Yohannes Desta, Lakshmikanth Namburi, Vincent E. Lopopolo, Sanjeev Grover, Erik Volkerink
  • Publication number: 20150233967
    Abstract: Example features or aspects of the present invention are described in relation to a small, quiet integrated cooling system for an apparatus for testing electronic devices. Characteristics of the test apparatus including a low noise output, low power consumption and a compact size with a small spatial and volume footprint are selected for deployment and use in a an office like environment. The test apparatus comprises a chassis frame and a cooler frame disposed within the chassis frame and thus integrated within the test apparatus, which has a reduced form factor suitable for the in-office deployment.
    Type: Application
    Filed: February 19, 2014
    Publication date: August 20, 2015
    Applicant: Advantest Corporation
    Inventors: Brent THORDARSON, John W. ANDBERG, Koei NISHIURA
  • Publication number: 20140070828
    Abstract: Disclosed herein is a cost effective, efficient, massively parallel multi-wafer test cell. Additionally, this test cell can be used for both single-touchdown and multiple-touchdown applications. The invention uses a novel “split-cartridge” design, combined with a method for aligning wafers when they are separated from the probe card assembly, to create a cost effective, efficient multi-wafer test cell. A “probe-card stops” design may be used within the cartridge to simplify the overall cartridge design and operation.
    Type: Application
    Filed: September 10, 2012
    Publication date: March 13, 2014
    Inventors: John W. Andberg, Ira H. Leventhal, Matthew W. Losey, Yohannes Desta, Lakshmikanth Namburi, Vincent E. Lopopolo, Sanjeev Grover, Erik Volkerink
  • Publication number: 20130135002
    Abstract: In one embodiment, an interface includes a plurality of test electronics to DUT interfaces. Each test electronics to DUT interface has at least one test electronics interface, at least one DUT interface, and an electrical coupling between the at least one test electronics interface and the at least one DUT interface. First and second subsets of the DUT interfaces are respectively positioned along the perimeters of first and second concentric shapes.
    Type: Application
    Filed: January 15, 2013
    Publication date: May 30, 2013
    Applicant: ADVANTEST (SINGAPORE) PTE LTD
    Inventors: Sanjeev Grover, Donald W. Chiu, John W. Andberg
  • Patent number: 8354853
    Abstract: In one embodiment, a test system has a set of test electronics for testing a device under test (DUT). The test system also has at least one test electronics to DUT interface having a zero insertion force (ZIF) connector. Each ZIF connector has a ZIF connector to DUT clamping mechanism configured to i) apply a first orthogonal force to a probe card that interfaces with a DUT, by pressing the ZIF connector against the probe card, and simultaneously ii) exert at least one second orthogonal force on the probe card, the at least one second orthogonal force being opposite in direction to the first orthogonal force.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: January 15, 2013
    Assignee: Advantest (Singapore) Pte Ltd
    Inventors: Sanjeev Grover, Donald W. Chiu, John W. Andberg
  • Publication number: 20100134134
    Abstract: In one embodiment, a test system has a set of test electronics for testing a device under test (DUT). The test system also has at least one test electronics to DUT interface having a zero insertion force (ZIF) connector. Each ZIF connector has a ZIF connector to DUT clamping mechanism configured to i) apply a first orthogonal force to a probe card that interfaces with a DUT, by pressing the ZIF connector against the probe card, and simultaneously ii) exert at least one second orthogonal force on the probe card, the at least one second orthogonal force being opposite in direction to the first orthogonal force.
    Type: Application
    Filed: November 25, 2009
    Publication date: June 3, 2010
    Inventors: Sanjeev Grover, Donald W. Chiu, John W. Andberg
  • Patent number: 7459921
    Abstract: A paddle board probe card for connecting a device under test with an ATE tester by means of ZIF connectors is presented. The paddle board probe card may include more than one printed circuit board mounted on a probe card in such a manner that the more than one printed circuit boards mate with ZIF connectors on an ATE testhead interface.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: December 2, 2008
    Assignee: Verigy (Singapore) Pte. Ltd.
    Inventors: Romi Mayder, John W. Andberg
  • Publication number: 20070296424
    Abstract: A paddle board probe card for connecting a device under test with an ATE tester by means of ZIF connectors is presented. The paddle board probe card may include more than one printed circuit board mounted on a probe card in such a manner that the more than one printed circuit boards mate with ZIF connectors on an ATE testhead interface.
    Type: Application
    Filed: May 31, 2006
    Publication date: December 27, 2007
    Inventors: Romi Mayder, John W. Andberg
  • Patent number: 7147499
    Abstract: In one embodiment, a mating circuit assembly is coupled and decoupled to a system by 1) mechanically and electrically coupling at least a first interposer, mounted on at least one of first and second substrates, to the mating circuit assembly. The mechanical and electrical coupling is accomplished using at least first and second spring mechanisms, with the first and second spring mechanisms being mounted between the connector housing and respective ones of the first and second substrates. At least one of the first and second substrates transmits signals between the first interposer and the system. The first interposer is electrically and mechanically decoupled from the mating circuit assembly by creating a vacuum between the connector housing and at least one of the first and second substrates. Other embodiments are also disclosed.
    Type: Grant
    Filed: October 19, 2005
    Date of Patent: December 12, 2006
    Assignee: Verigy IPco
    Inventors: Romi Mayder, John W. Andberg, Don Chiu, Noriyuki Sugihara
  • Patent number: 6140616
    Abstract: A thermal chuck or heat sink (10) has a lower surface (12) covered with fins (14) parallel to air flow (16), to increase the surface area and promote heat transfer. A pair of slots (32) near pedestal (20) (along the fins) effectively lowers the conductivity of the metal in the direction across the fins. Heat flowing through this region of lowered conductivity experiences a greater temperature drop. This raises the temperature at the adjacent parts of the top surface, and (for properly sized slots) results in circular isotherms. The circular isotherms are turned into a nearly isothermal surface by a precisely dimensioned groove (36) parallel to the top surface (22), extending around the circumference of the pedestal (20). Heat flowing into the outer regions of the circular surface (22) is forced to travel radially inward, thus raising the edge temperature (which would naturally be lower than the center).
    Type: Grant
    Filed: September 25, 1998
    Date of Patent: October 31, 2000
    Assignee: AEHR Test Systems
    Inventor: John W. Andberg