Abstract: A security arrangement for a telecommunications system having two security planes, a plurality of peripherals, a plurality of peripheral communication controllers; and switching arrangements interconnecting the peripheral communication controllers. To determine a faulty security plane, a duplex path is provided between the controllers, and, using this path, a controller automatically performs path checks on one of the security planes. If the plane is found to be not faulty, the controller sends data associated with that plane to the peripheral with which it is in communication.

Abstract: A number of methods are used in the prior art to provide speech sample security in a duplicated switch plane telecommunications switching system and these fall into three categories; (i) use the switching planes in a main/standby mode with errors detected by a check code accompanying the speech sample on the plane in use detected errors cause the standby to be switched-to, (ii) transmit speech across both planes simultaneously and compare and (iii) as per (ii) accompanied by a check code to identify the plane at fault. Categories (i) and (iii) require "extra" routes to transmit the check code whereas category (ii) can not detect which sample is in error. In serial transmission switch planes there are no "spare" routes available without creating extra routes for the check code alone. The basic principle of the invention is to pass the speech through one plane only which is known as the "biased to" plane. A checkcode is passed through the other "biased from" plane.

Abstract: The digital switchblock includes a plurality of processor clusters which communicate via peripheral interface buffers with a number of controllers connected in serial configuration and which further communicate with the switchblock. The switchblock has a number of receive digital switching modules connected to incoming PCM transmission channels and a number of transmit digital switching modules connected to outgoing PCM transmission channels. The receive and transmit digital switching modules are interconnected by way of a plurality of control digital switching modules, to which are connected all controllers. The interconnection between one receive digital switching module and one transmit digital switching module is set up by way of one central digital switching module by use of a plurality of control switch state maps stored in the controllers. The maps depict the current state of all digital switching modules and identify a connection path through the switchblock.