Patents by Inventor John W. Bodnar

John W. Bodnar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method for accessing a synchronous serial memory having unknown address bit field size
    Patent number: 7542365
    Abstract: An apparatus and method are provided for accessing a serial memory without knowing the required number of address bits. The apparatus comprises a pull circuit, a data out control circuit and a transition detector. The pull circuit causes the input terminal to be set to a first predetermined logic state in response to a read command being provided to the serial memory. The data out control circuit has an output terminal for providing the read command and a first predetermined number of address bits to the output terminal. The transition detector is coupled to an input terminal for detecting if the input terminal transitions from the first predetermined logic state to a second predetermined logic state in response to the first predetermined number of address bits. The transition detector will detect a transition of the input terminal when a correct number of address bits have been provided.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: June 2, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventor: John W. Bodnar
  • APPARATUS AND METHOD FOR ACCESSING A SYNCHRONOUS SERIAL MEMORY HAVING UNKNOWN ADDRESS BIT FIELD SIZE
    Publication number: 20090089530
    Abstract: An apparatus and method are provided for accessing a serial memory without knowing the required number of address bits. The apparatus comprises a pull circuit, a data out control circuit and a transition detector. The pull circuit causes the input terminal to be set to a first predetermined logic state in response to a read command being provided to the serial memory. The data out control circuit has an output terminal for providing the read command and a first predetermined number of address bits to the output terminal. The transition detector is coupled to an input terminal for detecting if the input terminal transitions from the first predetermined logic state to a second predetermined logic state in response to the first predetermined number of address bits. The transition detector will detect a transition of the input terminal when a correct number of address bits have been provided.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 2, 2009
    Inventor: John W. Bodnar
  • Digital simulation of organismal growth
    Patent number: 5621671
    Abstract: The growth and development of a biological organism reflected as a series of molecular and cellular processes by chromatin switching networks, form threshold mechanisms applied through simulation transcription rules to pattern formations of a digital approximation of regulator concentration gradient. Digital logic statements are derived from such pattern formations to simulate the growth and development of the organism.
    Type: Grant
    Filed: March 17, 1995
    Date of Patent: April 15, 1997
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: John W. Bodnar