Abstract: The invention provides various improved sailboats and methods for their use. In one exemplary embodiment, a sailboat comprises a hull and a deck that is operably attached to the hull. The deck has a longitudinal axis extending along its center. A mast is generally aligned with the longitudinal axis, and a luff cable is coupled to the mast and the deck. The luff cable is movable relative to the longitudinal axis. Further, a foresail is coupled to the luff cable such that at least a portion of the foresail is movable relative to the longitudinal axis upon movement of the luff cable.

Abstract: The invention provides various improved sailboats and methods for their use. In one exemplary embodiment, a sailboat comprises a hull and a deck that is operably attached to the hull. The deck has a longitudinal axis extending along its center. A mast is generally aligned with the longitudinal axis, and a luff cable is coupled to the mast and the deck. The luff cable is movable relative to the longitudinal axis. Further, a foresail is coupled to the luff cable such that at least a portion of the foresail is movable relative to the longitudinal axis upon movement of the luff cable.

Abstract: The invention provides various improved sailboats and methods for their use. In one exemplary embodiment, a sailboat comprises a hull and a deck that is operably attached to the hull. The deck has a longitudinal axis extending along its center. A mast is generally aligned with the longitudinal axis, and a luff cable is coupled to the mast and the deck. The luff cable is movable relative to the longitudinal axis. Further, a foresail is coupled to the luff cable such that at least a portion of the foresail is movable relative to the longitudinal axis upon movement of the luff cable.

Abstract: An error injection test scripting system that permits a test engineer to select from a series of commands those that will induce a desired test scenario. These commands are presented to a parser, either in command line form or as a batch of commands, which parses the syntax of the commands and associated parameters, to create a task list which is communicated to a scheduler. The scheduler handles the execution of the tasks in the list, converts parameters to explicit logical block test sequences and maintains test results. Tasks such as error injection use a special protocol (which the unit under test must be able to understand and interpret) to circumvent standard bus and controller protocols, so that test data, such as corrupt parity or multiple hard error failures can be sent to the disks in the RAID system, while bypassing the RAID array management functions that would otherwise automatically correct or prevent the errors.

Abstract: A peripheral device controller has an EEPROM which stores microinstructions to be placed in a random access memory control store. The EEPROM also stores peripheral configuration information. This information is obtained by polling the peripheral devices connected to the controller and storing the resulting information in the EEPROM. Upon powering up, the microinstructions stored in the EEPROM are transferred to the control store via execution of instructions held in a boot PROM. The controller, therefore, provides a fast control store while maintaining permanence of the microinstructions after power is extinguished. Means are also provided to update the control store and EEPROM. The EEPROM may upon CPU command be updated with new microinstructions held in main memory or obtained from peripheral devices.

Abstract: A plurality of units which are coupled to transfer requests, transfer data over an asynchronous bus network during allocated bus transfer cycles. The network has a tie-breaking bus priority network which is distributed to a common interface portion of each of the plurality of units and grants bus cycles and resolves simultaneous requests on a priority basis. At least one unit includes bus saturation detection apparatus included within its common interface portion for monitoring bus activity over established intervals of time. The detection of the occurrence of at least one available cycle over the given interval of time signals that the bus network is not in a saturated state. When the indicator specifies that the bus network is saturated, the unit throttles down its operation by increasing the amount of time between issuing data requests. Throttling continues until the bus is no longer being saturated.

Abstract: A controller connected between a system bus and peripheral devices has at least two microprocessors. One controls the data transfers with the peripheral devices, and the other controls data transfers with the system bus. The microprocessors share a data buffer and control store. This sharing is possible because of the controller timing means which synchronizes exclusive access to the shared components of the controller. When first initialized, the microprocessors are directed to execute a test instruction which points them to the beginning of their set of microinstructions. Once pointed to their set of microinstructions, normal operation may begin.

Abstract: A controller controls data transfers between a data processing system bus and peripheral devices. In the controller, data buffers are divided into page frames. Paging circuitry provides for allocation and deallocation of pages to and from the data buffer. Included in the page circuitry is a paging RAM. The paging RAM and other paging circuitry components allow contiguously addressed pages of data to be stored in noncontiguous locations in the data buffer. There may be more than one data buffer and these data buffers may be exclusively seized by microprocessors in the controller via seizing logic.

Abstract: A disk controller address register is used to address both a disk controller memory and a system memory between which data is transferred as it is stored on or retrieved from a disk storage device. A single address is provided to the address register which then develops other addresses needed in the data transfer between the two memories.

Abstract: Information read from a disk device includes synchronization bytes to enable a controller to get into byte synchronization with a stream of bits received from the disk. The stream of bits passes through a shift register. Firmware conditions a multiplexer which receives the parallel output of the serial register to select the high order binary ONE bit thereby enabling the controller to get into byte synchronization with the stream of bits.

Abstract: A sun visor for the rear seat side window made of relatively thin plastic or the like and being of substantially rectangular shape adapted to be mounted for support by the conventional coat hanger hook secured in the headliner of an automotive vehicle with the visor movable rotatably on said hook into and out of use position. The visor in its preferred embodiment can also be shifted axially relative to the hook, into desired position relative to the side of the vehicle on which it is mounted.