Abstract: Various embodiments include a memory device that is capable of being configured with a wide data bus interface or a narrow data bus interface. The wide data bus interface is suitable for low-cost applications, such as smart phones and laptop computers. The narrow data bus interface is suitable for applications where high memory density is desirable, such as data servers in a data center. The wide data bus is twice the width of the narrow data bus width. In the narrow data bus configuration, the memory device transfers twice the number of data words in a single burst transfer relative to the wide data bus width configuration. As a result, the number of bits transferred in a single burst transfer is the same regardless of the configuration, thereby simplifying control logic of the memory device. The memory device can further accommodate various packaging options that facilitate high density memory designs.

Abstract: A cowboy hat with interior head protection includes a hat, a helmet shell attached to the interior of the hat, and a ratchet adjustment assembly coupled to the helmet shell, wherein the helmet shell is substantially concealed within the interior of the hat.

Abstract: A cowboy hat with interior head protection includes a hat, a helmet shell attached to the interior of the hat, and a ratchet adjustment assembly coupled to the helmet shell, wherein the helmet shell is substantially concealed within the interior of the hat.

Abstract: A direct-to-digital software defined radar system includes a high-speed digitizer coupled directly to a receive antenna and outputs a digital signal to a processor which receives the digitized signal, along with an arbitrarily-defined reference signal provided by signal generator, and indexes the signal data according to time and geo-location, arranges the data according to a three-dimensional data structure, declutters and filters and refines the data for storage or display.

Abstract: An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.

Abstract: A direct-to-digital software defined radar system includes a high-speed digitizer coupled directly to a receive antenna and outputs a digital signal to a processor which receives the digitized signal, along with an arbitrarily-defined reference signal provided by signal generator, and indexes the signal data according to time and geo-location, arranges the data according to a three-dimensional data structure, declutters and filters and refines the data for storage or display.

Abstract: An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.

Abstract: An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.

Abstract: A method and system of providing access to a shared memory interconnected to a first controller and a second controller via a bus, the bus having control signals associated therewith for data transfer control and communication between the first and the second controllers. The second controller transmits an access request to the first controller for control of the bus to access the memory. The first controller selectively grants the access request and transmits an acknowledge to the second controller; and upon receiving the acknowledge, the second controller accesses the memory for data transfer. The first controller has a first priority for accessing the memory, and the second controller has a second priority for accessing the memory, the second priority being lower than the first priority such that upon request the first controller selectively grants control of the bus to the second controller for memory access, otherwise the first controller maintains control of the bus for memory access.