Abstract: A pattern plating method for fabricating printed circuit boards begins by bonding a thin layer of copper (e.g., copper foil) to the surface of the board. A photoresist layer is laminated over the copper layer, and then selectively exposed and developed to define a desired pattern of traces. A thick, second layer of copper is deposited on the traces by electrolytic deposition, and the photoresist is then removed. The board is etched with a solution containing cupric chloride (or an ammoniacal etchant) to remove those portions of the first copper layer that are not covered by the second copper layer. The present invention also allows through-holes to be drilled at selected locations after the first layer of copper foil has been bonded to the board. A thin layer of copper is then deposited by electroless deposition to create a conductive surface in the through-holes necessary for the subsequent step of electrolytic deposition in the process above.

Abstract: A local area network (LAN) system is provided that is capable of accommodating a variety of computer subsystem types, and having a LAN controller which can control at substantially the same time a plurality of LANs of the same type or a plurality of different types of LANs.

Abstract: An error detection system is disclosed for not only indicating but eliminating certain errors which may occur during the transfer of information between communication busses in a data processing system wherein plural communication busses each provide a common information path to plural data processing units including memory units, peripheral control units, central processing units and ISL units, and wherein each of the plural communication busses are in electrical communication with an ISL unit, and ISL units are electrically connected in pairs. The error detection system requires no special supporting software or firmware on the part of any data processing unit on any of the communication busses.

Abstract: A logic system is provided for accommodating the exchange of information between two or more communication busses of a data processing system, wherein plural central processing units and plural memory units on independent communication busses may have same logic addresses. Memory and CPU addresses are translated at the bus rate through a multiplicity of flexible address translation ranges to enable a data processing unit on one communication bus to access an apparent contiguous range of addresses encompassing all data processing units on all communication busses.

Abstract: An intersystem communication control system in an intersystem link (ISL) unit is provided to accommodate the simultaneous bidirectional transfer of binary coded information between communication busses in a data processing system, wherein the plural communication busses are electrically interconnected by ISL unit twins, and information may be transferred between plural communication busses asynchronously.

Abstract: A logic control system in an intersystem link (ISL) unit accommodating the transfer of binary coded information between communication busses in a data processing system is disclosed, wherein information may be transferred between plural communication busses while further information flow continues on each communication bus at the bus rate, and additional information transfers between the communication busses continue to be handled by the ISL unit.

Abstract: A logic control system in an intersystem link (ISL) unit accommodating the transfer of binary coded information between communication busses in a data processing system is disclosed, wherein an ISL unit may be reconfigured to reallocate communication bus resources without incurring excessive software overhead time losses.

Abstract: A logic control system is disclosed for verifying the operability of memory and non-memory data and control paths in both local and remote intersystem link (ISL) units electrically interconnecting a local and remote communication bus in a data processing system. The data processing system may include two or more communication busses each pair of which are electrically interconnected by twin ISL units. The control logic architecture accommodates the receipt of a test mode command from a CPU on a local bus to initiate a test mode operation wherein the memory and non-memory data and control paths of both the local and the remote ISL units are excerised while on-line, and binary coded information received from the local bus is passed through the ISL units, onto the remote bus, and returned to a local bus memory resource for verification. No remote bus resources are used or affected, and the remote ISL unit shall ignore any communications received from any other data processing unit on the remote bus.

Abstract: A logic system in an intersystem link (ISL) unit accommodating the transfer of binary coded information between communication busses in a data processing system is disclosed, wherein dedicated locations in a file register are selected at the bus rate in response to binary coded information received from a local communication bus. ISL transactions to be initiated in response to bus cycle requests thereby are identified. ISL transactions are handled in parallel, and memory transfers are segregated from non-memory transfers to avoid unnecessary delays in memory transfers.

Abstract: A logic system referred to as an intersystem link unit (ISL) is provided for accommodating the transfer of binary coded information between two or more communication busses in a data processing system, wherein information including memory and non-memory read and write requests, CPU to CPU interrupts, peripheral control units to CPU interrupts may be transferred between plural communication busses each supporting plural data processing units including plural CPUs without substantially affecting the bus rate of the individual communication busses. Binary coded information from a communication bus is acquired asynchronously, and plural bus communications of different types are accommodated in parallel. The ISL units further may be dynamically reconfigured to provide for a reallocation of communication bus resources between communication busses.

Abstract: A logic system in an intersystem link (ISL) unit is provided for avoiding deadlock conditions which may occur in a data processing system wherein multiple CPUs on one communication bus attempt to communicate with resources on remote communication busses.The data processing system has plural communication busses, each providing a common information path to plural data processing units including memory units, peripheral control units, central processing units (CPUs) and ISL units, and each of the plural communication busses are in electrical communication with an ISL unit, and ISL units are electrically connected in pairs.

Abstract: An attachment for a motorized cart comprising an adjustable bracket which may be mounted on suitable support arms which extend rearwardly of the cart. The bracket is adapted to retain an umbrella or like canopy in adjusted position so as to extend over the occupants of the cart and also over a storage area which is provided rearwardly of the seating area for the occupants of the cart.

Abstract: A central processing system which includes a plurality of units coupled over a common electrical bus for the transfer of information between any two units, includes one unit in which there is a shareable resource such as a memory for example. Apparatus is provided for any units to share such resource. Further apparatus is provided for enabling any of such units so sharing the resource to lock out any other unit which presents a specified control signal to the unit incorporating the resource.

Abstract: In a data processing system which includes a common bus to which a plurality of units are connected for the transfer of information, information may be transferred by the highest priority requesting unit during an asynchronously generated bus transfer cycle. Logic is provided for enabling a split bus cycle operation in which the master unit requesting information from the slave unit during a first bus transfer cycle may receive such information from the slave unit during a later slave generated bus transfer cycle. Means are provided for enabling any other units to communicate over the common bus during the time between the first cycle and such later cycle during which the slave unit responds, thereby enabling at least two pairs of units to communicate with each other respectively in an interleaved manner.

Abstract: In a data processing system having a plurality of units coupled for the transfer of information therebetween over a common electrical bus during asynchronously generated information bus transfer cycles, the units are coupled in a priority network and depending upon their respective priority may gain access to the bus before a lower priority unit is so enabled. Each one of the units includes apparatus for responding to a request for the transfer of information from another unit by providing any one of up to three signal responses including a positive acknowledge signal indicating an immediate response, a negative acknowledge signal indicating that the unit will most likely be busy for a relatively extended period of time and a quasi-negative response indicating that the unit will probably be ready during the next asynchronously generated bus transfer cycle.