Abstract: A method for testing floating point hardware in a processor while executing a computer program is disclosed. The method includes executing a first set of code of the computer program without employing the floating point hardware. The first set of code has a first floating point operation, thereby obtaining an emulated result. The method also includes executing the first floating point instruction utilizing the floating point hardware, thereby obtaining a hardware-generated result. The method also includes comparing the emulated result with the hardware-generated result.

Abstract: A computer-executable method for analyzing a condition of a computer system comprises executing an operating system on a processor according to an operating system image resident in a memory, and executing an analysis engine independently of the operating system on the processor in co-existence with the operating system. The analysis engine is enabled complete access to information relating to the processor and the operating system. The operating system is prevented access to the analysis engine.

Abstract: A method for synchronizing a plurality of processors of a multi-processor computer system on a synchronization point is disclosed. The method includes triggering a first set of processors, using a lead processor of the plurality of processors when the lead processor encounters the synchronization point, to enter an exit holding loop. The first set of processors representing the plurality of processors except the lead processor. The triggering the first set of processors is performed without accessing a shared memory area of the multi-processor system. There is also included triggering the plurality of processors, using a tail processor of the plurality of processors when the tail processor encounters the synchronization point, to leave the exit holding loop. The triggering the plurality of processors is performed without accessing the shared memory area of the multi-processor system.

Abstract: A computer-executable method for analyzing a condition of a computer system comprises executing an operating system on a processor according to an operating system image resident in a memory, and executing an analysis engine independently of the operating system on the processor in co-existence with the operating system. The analysis engine is enabled complete access to information relating to the processor and the operating system. The operating system is prevented access to the analysis engine.

Abstract: A computer-implemented method for monitoring a computer system when the computer system executes a user application using a production operating system (OS) is disclosed. The method includes providing a diagnostic monitor, the diagnostic monitor being configured to be capable of executing even if the OS kernel fails to execute, the diagnostic monitor having a monitor trap arrangement. If a trap is encountered during execution of the user application, the method includes ascertaining using the diagnostic monitor whether the trap is to be handled by the OS kernel or the diagnostic monitor. If the trap is to be handled by the OS kernel, the method includes passing the trap to the OS kernel for handling.

Abstract: A computer-implemented method for diagnosing the performance of a computer system using a diagnostic application. The method includes providing a diagnostic application and providing an operating system (OS) kernel, the diagnostic application being configured to execute under the OS kernel in the computer system, the OS kernel having a kernel trap arrangement. The method also includes providing a diagnostic monitor, the diagnostic monitor being configured to execute cooperatively with the OS kernel, the diagnostic monitor having a monitor trap arrangement. The method additionally includes ascertaining, using the diagnostic monitor, whether a trap encountered during execution of the diagnostic application is to be handled by the OS kernel or the diagnostic monitor. Furthermore, the method includes passing, if the trap is to be handled by the OS kernel, the trap to the OS kernel for handling.

Abstract: A computer-implemented method for diagnosing the performance of a computer system using a diagnostic application. The method includes providing a diagnostic application and providing an operating system (OS) kernel, the diagnostic application being configured to execute under the OS kernel in the computer system, the OS kernel having a kernel trap arrangement. The method also includes providing a diagnostic monitor, the diagnostic monitor being configured to execute cooperatively with the OS kernel, the diagnostic monitor having a monitor trap arrangement. The method additionally includes ascertaining, using the diagnostic monitor, whether a trap encountered during execution of the diagnostic application is to be handled by the OS kernel or the diagnostic monitor. Furthermore, the method includes passing, if the trap is to be handled by the OS kernel, the trap to the OS kernel for handling.

Abstract: A computer-implemented method for monitoring a computer system when the computer system executes a user application using a production operating system (OS) is disclosed. The method includes providing a diagnostic monitor, the diagnostic monitor being configured to be capable of executing even if the OS kernel fails to execute, the diagnostic monitor having a monitor trap arrangement. If a trap is encountered during execution of the user application, the method includes ascertaining using the diagnostic monitor whether the trap is to be handled by the OS kernel or the diagnostic monitor. If the trap is to be handled by the OS kernel, the method includes passing the trap to the OS kernel for handling.

Abstract: A porous substrate curtain coated with a single coating of a liquid dielectric that is cured into a well adhering film at least 15 microns thick with a uniformity of less than 5 microns. The substrate is cleaned to remove contaminants, heated to remove moisture, curtain coated with a single coating of a viscous heat curable liquid dielectric such as polyimide, and heated to cure the dielectric by increasing the temperature at most 15.degree. C. per minute to a predetermined cure temperature not exceeding 450.degree. C. The invention is well suited for fabricating a dielectric layer in a high density multichip module.

Abstract: A defective metallization layer is removed from the top of an electronic component such as an integrated circuit or a copper/polyimide substrate by polishing with a rotating pad and a slurry. Non-defective underlying metallization layers are preserved and a new metallization layer is fabricated to replace the defective layer.

Abstract: A method for fabricating metal pillars in an electronic component. The method includes providing a base with spaced vias in a top surface, depositing an electrically conductive metal into the vias and over the top surface of the base so that a metal layer with an uneven top surface forms over the base, and planarizing the metal by polishing. The polishing can remove the entire metal layer leaving metal pillars in and aligned with the base. Or the polishing can be completed before removing the metal layer and metal above the base between the vias can be etched to form metal pillars with uniform heights which extend above the base. The invention is well suited for fabricating high-density multilayer copper/polyimide electrical interconnects.

Abstract: A method of reworking an electrical multilayer interconnect in which the electrical lines can be protected by an overcoat. The method includes removing a defective metallization layer from the top of an interconnect substrate, depositing an electrically conductive layer on the substrate, forming a base plating mask on the electrically conductive layer, plating a copper base into an opening in the base plating mask onto the electrically conductive layer, stripping the base plating mask, forming a pillar plating mask on top of the copper base, plating an electrically conductive metal pillar into an opening in the pillar plating mask onto the top of the copper base, stripping the plating mask, and stripping the electrically conductive layer below the stripped base plating mask. Additionally, a protective overcoat layer can be deposited on the exposed copper surfaces.