Abstract: A memory (30) includes input buffers (35, 38, 56), decoders (31, 32, 36), and a memory portion (34). The input buffers (35, 38, 56) include a delay circuit (82) which delays at least one transition of an input signal. The delay circuit (82) includes a compensation circuit (250) which compensates the delay circuit (82) for voltage, temperature, and processing variations. In one embodiment, the delay circuit (82) includes a CMOS inverter (102, 103) with an additional transistor (101) coupled between a source of an inverter transistor (102) and a corresponding power supply voltage. The compensation circuit (250) provides a bias voltage to bias a gate of the transistor (101) to determine the delay of the delay circuit (82). The compensation circuit (250) provides the bias voltage as that voltage which biases the transistor (101) to conduct a precision reference current.

Abstract: A BICMOS NAND gate (40) has a CMOS NAND gate (41), a bipolar pull-up transistor (47), a bipolar pull-down transistor (48), series connected N-channel transistors (43-45) coupled between the base and collector of pull-down transistor (48), N-channel transistors (42, 46, 49, and 50), and a V.sub.BG generated reference voltage (51). N-channel transistor (46) receives a variable bias voltage provided by transistors 49, 50, and V.sub.BG generated reference voltage (51). At high power supply voltages, N-channel transistor (46) prevents pull-down transistor (48) from becoming saturated when BICMOS NAND gate (40) is operating at high frequency, when an input becomes skewed, or a glitch develops, yet allows for satisfactory operation BICMOS NAND gate (40) at low power supply voltages.