Abstract: A method and apparatus are provided for managing cache allocation for a plurality of data types in a unified cache having dynamically allocable lines for first type data and for second type data. Cache allocation is managed by counting misses to first type data and misses to second type data in the unified cache, and by determining when a difference between a number of first type data misses and a number of second type data misses crosses a preselected threshold. A replacement algorithm of the unified cache then is adjusted in response to the detected crossing of the preselected threshold, the adjusting step including increasing a replacement priority of the first type data lines in the cache. The replacement algorithm preferably is an LRU algorithm wherein the adjusting step includes incrementing an age indication of the first type data lines.

Abstract: A method for tracking multiple injured victims at a multiple injury scene to provide information on their medical status and their location to emergency personnel and to treatment facilities, the method including examining the injured victims at the scene to determine the medical condition of the victims, attaching a tag to each of the victims to identify the victim and to indicate the medical condition of the victim, the tag having machine-readable information thereon indicating the identity and medical condition of the victim, and the tag having visually readable colors thereon indicating the urgency of treatment needed by the victim, scanning and transmitting the machine-readable information on each of the victims to victim transportation units and other emergency personnel at the scene to enable transport personnel to determine which victims are in most urgent need of transport to a medical treatment facility, and transmitting the machine-readable information on each of the victims to medical treatment fa

Abstract: A processor system is provided that comprises a plurality of L0 caches, a processor having a plurality of execution units, and an L1 cache for caching any data and instructions used by the processor. A portion of the execution units provided are configured so that each execution unit within the portion accesses one of the L0 caches. Each of the L0 caches is accessible by only one of the portion of the execution units, and each L0 cache caches a subset of any data used by the processor which is not cacheable by any of the other L0 caches. The processor system preferably comprises an instruction dispatcher that dispatches instructions executable by the processor and that selectively designates data as cacheable by only one of the L0 caches, preferably at dispatch time.

Abstract: A method for tracking multiple injured victims at a multiple injury scene to provide information on their medical status and their location to emergency personnel and to treatment facilities, the method including examining the injured victims at said scene to determine the medical condition of said victims, attaching a tag to each of said victims to identify said victim and to indicate said medical condition of said victim, said tag having machine-readable information thereon indicating the identity and medical condition of said victim, and said tag having visually readable colors thereon indicating the urgency of treatment needed by the victim, scanning and transmitting said machine-readable information on each of said victims to victim transportation units and other emergency personnel at said scene to enable transport personnel to determine which victims are in most urgent need of transport to a medical treatment facility, and transmitting said machine-readable information on each of said victims to medica

Abstract: A method for tracking multiple injured victims at a multiple injury scene to provide information on their medical status and their location to emergency personnel and to treatment facilities, the method including examining the injured victims at the scene to determine the medical condition of the victims, attaching a tag to each of the victims to identify the victim and to indicate the medical condition of the victim, the tag having machine-readable information thereon indicating the identity and medical condition of the victim, and the tag having visually readable colors thereon indicating the urgency of treatment needed by the victim, scanning and transmitting the machine-readable information on each of the victims to victim transportation units and other emergency personnel at the scene to enable transport personnel to determine which victims are in most urgent need of transport to a medical treatment facility, and transmitting the machine-readable information on each of the victims to medical treatment fa

Abstract: A microprocessor which supports two distinct instruction-set architectures. The microprocessor includes a mode control unit which enables extensions and/or limitations to each of the two architectures and controls the architectural context under which the microprocessor operates. The control unit controls memory management unit (MMU) hardware that is designed to allow address translation to take place under the control of a mode bit so that the translation mechanism can be switched from one architecture to another. A single MMU translates addresses of the two distinct architectures under control of the mode bit which is also used to simultaneously inform instruction decode which architecture is being used so that instructions are properly decoded. The MMU is also capable of mapping the address translation of one architecture onto that of the other so that software written for both architectures may be multi-tasked under the control of a single operating system.

Abstract: A system for optimizing a logic network including expressing the logic network as an original graph having vertices, edges which connect the vertices and which represent connections in the logic network, and inversion markings for representing inverters in the logic network; determining a fundamental cycle(s) in the original graph; sorting the determined fundamental cycle(s) according to its parity; forming a final graph by processing the fundamental cycle(s) so as to optimize inverter placement therein while maintaining the parity thereof; comparing the inversion markings of the original and final graphs to determine a set of transformation locations in the logic network; and re-configuring the logic network in accordance with the determined transformation locations.