Abstract: A method and system, the method including, in some embodiments, calculating, by a message originator, a first check sum byte, appending the first check sum byte to the message, sending the message from the originator to a client over a single wire serial bus, and determining, by the client, a validity of the message from the originator by comparing the first check sum byte with a second check sum calculated by the client.

Abstract: A method for a mechanism for processor power state aware distribution of lowest priority interrupts. The method of one embodiment comprises receiving first power state information from a first component and second power state information from a second component. First task priority information from the first component and second task priority from the second component are also received. An interrupt request from a first device for servicing is received. Power state and task priority information for the first and second components are evaluated to determine which component should service the interrupt request. Either the first component or the second component is selected to be a destination component to service the interrupt request based on the power state and task priority information. The interrupt request is communicated to the destination component.

Abstract: A method and device are provided to monitor clock control signals from a CPU core; and calculate a time period during a sampling interval that the CPU core was used to perform work based on the clock control signals.

Abstract: A computer system having one or more components capable of being in either wake or sleep states includes a power manager and a voltage regulator. The power manager may generate a power state signal indicating the power state of the component, and this signal may be provided to the voltage regulator. The voltage regulator may supply power to the component. The target voltage level of the power may be dependent on both a current level of the power and the power state signal.

Abstract: A method and system, the method including, in some embodiments, calculating, by a message originator, a first check sum byte, appending the first check sum byte to the message, sending the message from the originator to a client over a single wire serial bus, and determining, by the client, a validity of the message from the originator by comparing the first check sum byte with a second check sum calculated by the client.

Abstract: In accordance with an embodiment of the present invention, a triggering event is initiated to place a processor in a low power state. The processor may or may not flush a cache upon entering the low power state depending on a power status signal. The power status signal may indicated the relative priority of power reduction associated with placing the processor in the low power state without first flushing the cache versus an increase in soft error rate in the cache associated with reducing the voltage in the low power state.

Abstract: A processor provides a configured clock rate setting for use by a peripheral set. The processor receives back from the peripheral set a feedback clock rate setting. The configured clock rate setting and the feedback clock rate setting are compared to detect over-clocking of the processor.

Abstract: A method for a mechanism for processor power state aware distribution of lowest priority interrupts. The method of one embodiment comprises receiving first power state information from a first component and second power state information from a second component. First task priority information from the first component and second task priority from the second component are also received. An interrupt request from a first device for servicing is received. Power state and task priority information for the first and second components are evaluated to determine which component should service the interrupt request. Either the first component or the second component is selected to be a destination component to service the interrupt request based on the power state and task priority information. The interrupt request is communicated to the destination component.

Abstract: An apparatus for using fluid laden with nanoparticles for application in electronic cooling is described. In one embodiment, an electromagnetic pump is used to circulate the nanoparticle laden fluid.

Abstract: A computer system having one or more components capable of being in either wake or sleep states includes a power manager and a voltage regulator. The power manager may generate a power state signal indicating the power state of the component, and this signal may be provided to the voltage regulator. The voltage regulator may supply power to the component. The target voltage level of the power may be dependent on both a current level of the power and the power state signal.

Abstract: In accordance with an embodiment of the present invention, a triggering event is initiated to place a processor in a low power state. The processor may or may not flush a cache upon entering the low power state depending on a power status signal. The power status signal may indicate the relative priority of power reduction associated with placing the processor in the low power state without first flushing the cache versus an increase in soft error rate in the cache associated with reducing the voltage in the low power state.

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a first clock receiver, one or more clock traces coupled to the clock generator, and clock generator coupled to the one or more clock traces. The clock generator gates clock signals to the first clock receiver in response to detecting that the clock traces have been disconnected from electrical ground.

Abstract: A method and an apparatus for lossless clock domain translation for a pixel stream have been disclosed. The method includes generating a first pixel stream on a first clock signal, the first clock signal being from a first source, forwarding a second clock signal from a second source and the first pixel stream to a buffer to translate the first pixel stream into a second pixel stream on the second clock signal, and providing a feedback to the second source to cause the second source to adjust the center frequency of the second clock signal to match the average frequency of the first clock signal with the average frequency of the second clock signal.

Abstract: An integrated circuit (IC) package includes a substrate, a ground line, and an encoded region. The encoded region provides information based upon selective deposition of solder balls electrically coupled to the ground line.

Abstract: A method for a mechanism for processor power state aware distribution of lowest priority interrupts. The method of one embodiment comprises receiving first power state information from a first component and second power state information from a second component. First task priority information from the first component and second task priority from the second component are also received. An interrupt request from a first device for servicing is received. Power state and task priority information for the first and second components are evaluated to determine which component should service the interrupt request. Either the first component or the second component is selected to be a destination component to service the interrupt request based on the power state and task priority information. The interrupt request is communicated to the destination component.

Abstract: Embodiments of the invention include a system for driving a slave device of a serial bus when the serial bus is otherwise unused. A bus mastering device, which can be a CPU, controls a data line and a clock line of the serial bus. The bus mastering device sends a command to the slave device over the data line, and then drives the clock line of the serial bus with a clock signal. The slave device accepts the clock signal, and uses it as a clock signal to drive functions of the slave device. Existing serial bus standards may be maintained, or proprietary bus standards can be used.

Abstract: A method and device are provided to monitor clock control signals from a CPU core; and calculate a time period during a sampling interval that the CPU core was used to perform work based on the clock control signals.

Abstract: A computer system having one or more components capable of being in either wake or sleep states includes a power manager and a voltage regulator. The power manager may generate a power state signal indicating the power state of the component, and this signal may be provided to the voltage regulator. The voltage regulator may supply power to the component. The target voltage level of the power may be dependent on both a current level of the power and the power state signal.

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a first clock receiver, one or more clock traces coupled to the clock generator, and clock generator coupled to the one or more clock traces. The clock generator gates clock signals to the first clock receiver in response to detecting that the clock traces have been disconnected from electrical ground.

Abstract: An integrated circuit (IC) package includes a substrate, a ground line, and an encoded region. The encoded region provides information based upon selective deposition of solder balls electrically coupled to the ground line.