Patents by Inventor John W. Howson
John W. Howson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20260038187Abstract: An application sends primitives to a graphics processing system so that an image of a 3D scene can be rendered. The primitives are placed into primitive blocks for storage and retrieval from a parameter memory. Rather than simply placing the first primitives into a primitive block until the primitive block is full and then placing further primitives into the next primitive block, multiple primitive blocks can be “open” such that a primitive block allocation module can allocate primitives to one of the open primitive blocks to thereby sort the primitives into primitive blocks according to their spatial positions. By grouping primitives together into primitive blocks in accordance with their spatial positions, the performance of a rasterization module can be improved. For example, in a tile-based rendering system this may mean that fewer primitive blocks need to be fetched by a hidden surface removal module in order to process a tile.Type: ApplicationFiled: October 10, 2025Publication date: February 5, 2026Inventors: Xile Yang, John W. Howson, Jonathan Redshaw
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Publication number: 20250390976Abstract: A method and system for generating and shading a computer graphics image in a tile based computer graphics system is provided. Geometry data is supplied and a plurality of primitives are derived from the geometry data. One or more modified primitives are then derived from at least one of the plurality of primitives. For each of a plurality of tiles, an object list is derived including data identifying the primitive from which each modified primitive located at least partially within that tile is derived. Alternatively, the object list may include data identifying each modified primitive located at least partially within that tile. Each tile is then shaded for display using its respective object list.Type: ApplicationFiled: September 2, 2025Publication date: December 25, 2025Inventors: Steven J. Fishwick, John W. Howson
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Publication number: 20250384622Abstract: A graphics processing system includes hidden surface removal logic and processing logic for processing fragments. An early depth test is performed on a first fragment with the hidden surface removal logic using a depth buffer, the first fragment having a shader-dependent property. In response to the first fragment passing the early depth test, the processing logic determines the property of the first fragment. After the determination of the property of the first fragment, a late depth test is performed on the first fragment with the hidden surface removal logic using the depth buffer. After performing the early depth test on the first fragment but before the late depth test is performed on the first fragment, an early depth test is performed on a second fragment with the hidden surface removal logic, wherein the second fragment does not have a shader-dependent property.Type: ApplicationFiled: September 2, 2025Publication date: December 18, 2025Inventors: Panagiotis Velentzas, John W. Howson, Richard Broadhurst
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Publication number: 20250370977Abstract: A hierarchy is a multi-level linked structure of nodes, wherein the hierarchy represents data relating to a set of one or more items to be processed. Where there are multiple input hierarchies, it may improve the efficiency of the processing of the items to merge the input hierarchies to form a merged hierarchy. The hierarchies are merged by identifying two or more sub-hierarchies within the input hierarchies which are to be merged, and determining one or more nodes of the merged hierarchy which reference nodes of the identified sub-hierarchies. The determined nodes of the merged hierarchy are stored and indications of the references between the determined nodes of the merged hierarchy and the referenced nodes of the identified sub-hierarchies are also stored. In this way, the merged hierarchy is formed for use in processing the items.Type: ApplicationFiled: August 11, 2025Publication date: December 4, 2025Inventors: Matthew Harrison, John W. Howson, Luke T. Peterson, Steven J. Clohset
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Publication number: 20250349063Abstract: A method and system for performing a render using a graphics processing unit that implements a tile-based graphics pipeline where a rendering space is sub-divided into tiles. For a selected tile of a plurality of tiles, a representation of per-tile vertex shader data identifying vertex shader programs used to generate processed primitives located within the selected tile is stored, and it is determined whether the output of a previous render for the selected tile can be used as an output for the render, by comparing the per-tile vertex shader data of the selected tile of the render with that of the previous render.Type: ApplicationFiled: June 2, 2025Publication date: November 13, 2025Inventors: John W. Howson, Xile Yang, Maurizio Zucchelli
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Publication number: 20250349064Abstract: Methods and tiling engines for tiling primitives in a tile based graphics processing system. A multi-level hierarchy of tile groups is generated, each level comprising one or more tile groups comprising one or more of the plurality of tiles. A plurality of primitive blocks is received, each comprising geometry data for one or more primitives. Each of the plurality of primitive blocks is associated with one or more of the tile groups up to a maximum number of tile groups such that if at least one primitive of a primitive block falls, at least partially, within the bounds of a tile, the primitive block is associated with at least one tile group that includes that tile. A control stream is generated for each tile group based on the associations, wherein each control stream comprises a primitive block entry for each primitive block associated with the corresponding tile group.Type: ApplicationFiled: July 22, 2025Publication date: November 13, 2025Inventors: Diego Jesus, John W. Howson, Panagiotis Velentzas, Robert Brigg, Xile Yang
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Patent number: 12462464Abstract: An application sends primitives to a graphics processing system so that an image of a 3D scene can be rendered. The primitives are placed into primitive blocks for storage and retrieval from a parameter memory. Rather than simply placing the first primitives into a primitive block until the primitive block is full and then placing further primitives into the next primitive block, multiple primitive blocks can be “open” such that a primitive block allocation module can allocate primitives to one of the open primitive blocks to thereby sort the primitives into primitive blocks according to their spatial positions. By grouping primitives together into primitive blocks in accordance with their spatial positions, the performance of a rasterization module can be improved. For example, in a tile-based rendering system this may mean that fewer primitive blocks need to be fetched by a hidden surface removal module in order to process a tile.Type: GrantFiled: October 6, 2022Date of Patent: November 4, 2025Assignee: Imagination Technologies LimitedInventors: Xile Yang, John W. Howson, Jonathan Redshaw
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Publication number: 20250336138Abstract: A graphics processing unit having multiple groups of processor cores for rendering graphics data for allocated tiles and outputting the processed data to regions of a memory resource. Scheduling logic allocates sets of tiles to the groups to perform a first render, and at a time when at least one of the groups has not completed processing its allocated sets as part of the first render, allocates at least one set of tiles for a second render to one of the other groups for processing. Progress indication logic indicates progress of the first render, indicating regions of the memory resource for which processing for the first render has been completed. Progress check logic checks the progress indication in response to a request for access to a region of the memory resource as part of the second render and enables access to that region of the resource in response to an indication that processing for the first render has been completed for that region.Type: ApplicationFiled: July 7, 2025Publication date: October 30, 2025Inventors: John W. Howson, Steven J. Fishwick
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Publication number: 20250316014Abstract: A method of managing resources in a graphics processing pipeline includes, in response to selecting a task for execution within a texture/shading unit, allocating to the task both a static allocation of temporary registers for the entire task and a dynamic allocation of temporary registers. The dynamic allocation comprises temporary registers used by a first phase of the task only and the static allocation of temporary registers comprises any temporary registers that are used by the program and are live at a boundary between two phases. When the task subsequently reaches a boundary between two phases, the dynamic allocation of temporary registers are freed and a new dynamic allocation of temporary registers for a next phase of the task is allocated to the task.Type: ApplicationFiled: June 20, 2025Publication date: October 9, 2025Inventors: Panagiotis Velentzas, John W. Howson, Richard Broadhurst
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Patent number: 12406325Abstract: A method and system for generating and shading a computer graphics image in a tile based computer graphics system is provided. Geometry data is supplied and a plurality of primitives are derived from the geometry data. One or more modified primitives are then derived from at least one of the plurality of primitives. For each of a plurality of tiles, an object list is derived including data identifying the primitive from which each modified primitive located at least partially within that tile is derived. Alternatively, the object list may include data identifying each modified primitive located at least partially within that tile. Each tile is then shaded for display using its respective object list.Type: GrantFiled: March 4, 2024Date of Patent: September 2, 2025Assignee: Imagination Technologies LimitedInventors: Steven J. Fishwick, John W. Howson
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Patent number: 12406433Abstract: Methods and graphics processing units for processing a plurality of fragments in a graphics processing system. A received first fragment is processed by performing an early depth test with hidden surface removal logic using a depth buffer; in response to the first fragment passing the early depth test, executing one or more instructions of a shader program for the first fragment on the processing logic to determine the property of the first fragment; and after the determination of the property of the first fragment, performing a late depth test on the first fragment with the hidden surface removal logic using the depth buffer. After said receiving a first fragment, a second fragment to be processed is received, wherein the second fragment does not have a shader-dependent property. The second fragment is processed by, before said late depth test is performed on the first fragment, performing an early depth test on the second fragment with the hidden surface removal logic.Type: GrantFiled: June 22, 2023Date of Patent: September 2, 2025Assignee: Imagination Technologies LimitedInventors: Panagiotis Velentzas, John W. Howson, Richard Broadhurst
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Patent number: 12386806Abstract: A hierarchy is a multi-level linked structure of nodes, wherein the hierarchy represents data relating to a set of one or more items to be processed. Where there are multiple input hierarchies, it may improve the efficiency of the processing of the items to merge the input hierarchies to form a merged hierarchy. The hierarchies are merged by identifying two or more sub-hierarchies within the input hierarchies which are to be merged, and determining one or more nodes of the merged hierarchy which reference nodes of the identified sub-hierarchies. The determined nodes of the merged hierarchy are stored and indications of the references between the determined nodes of the merged hierarchy and the referenced nodes of the identified sub-hierarchies are also stored. In this way, the merged hierarchy is formed for use in processing the items.Type: GrantFiled: April 22, 2022Date of Patent: August 12, 2025Assignee: Imagination Technologies LimitedInventors: Matthew Harrison, John W. Howson, Luke T. Peterson, Steven J. Clohset
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Publication number: 20250252671Abstract: Methods and apparatus for generating a data structure for storing primitive data for a number of primitives and vertex data for a plurality of vertices, wherein each primitive is defined with reference to one or more of the plurality of vertices. The vertex data comprises data for more than one view, such as a left view and a right view, with vertex parameter values for a first group of vertex parameters being stored separately for each view and vertex parameter values for a second, non-overlapping group of vertex parameters being stored only once and used when rendering either or both views.Type: ApplicationFiled: April 23, 2025Publication date: August 7, 2025Inventor: John W. Howson
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Patent number: 12367634Abstract: A method of managing resources in a graphics processing pipeline includes, in response to selecting a task for execution within a texture/shading unit, allocating to the task both a static allocation of temporary registers for the entire task and a dynamic allocation of temporary registers. The dynamic allocation comprises temporary registers used by a first phase of the task only and the static allocation of temporary registers comprises any temporary registers that are used by the program and are live at a boundary between two phases. When the task subsequently reaches a boundary between two phases, the dynamic allocation of temporary registers are freed and a new dynamic allocation of temporary registers for a next phase of the task is allocated to the task.Type: GrantFiled: April 18, 2024Date of Patent: July 22, 2025Assignee: Imagination Technologies LimitedInventors: Panagiotis Velentzas, John W. Howson, Richard Broadhurst
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Patent number: 12367633Abstract: Methods and tiling engines for tiling primitives in a tile based graphics processing system in which a rendering space is divided into a plurality of tiles. The method includes generating a multi-level hierarchy of tile groups, each level of the multi-level hierarchy comprising one or more tile groups comprising one or more of the plurality of tiles; receiving a plurality of primitive blocks, each primitive block comprising geometry data for one or more primitives; associating each of the plurality of primitive blocks with one or more of the tile groups up to a maximum number of tile groups such that if at least one primitive of a primitive block falls, at least partially, within the bounds of a tile, the primitive block is associated with at least one tile group that includes that tile; and generating a control stream for each tile group based on the associations, wherein each control stream comprises a primitive block entry for each primitive block associated with the corresponding tile group.Type: GrantFiled: March 4, 2024Date of Patent: July 22, 2025Assignee: Imagination Technologies LimitedInventors: Diego Jesus, John W. Howson, Panagiotis Velentzas, Robert Brigg, Xile Yang
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Publication number: 20250225079Abstract: A method of GPU virtualization comprises allocating each virtual machine (or operating system running on a VM) an identifier by the hypervisor and then this identifier is used to tag every transaction deriving from a GPU workload operating within a given VM context (i.e. every GPU transaction on the system bus which interconnects the CPU, GPU and other peripherals). Additionally, dedicated portions of a memory resource (which may be GPU registers or RAM) are provided for each VM and whilst each VM can only see their allocated portion of the memory, a microprocessor within the GPU can see all of the memory. Access control is achieved using root memory management units which are configured by the hypervisor and which map guest physical addresses to actual memory addresses based on the identifier associated with the transaction.Type: ApplicationFiled: March 25, 2025Publication date: July 10, 2025Inventors: Dave Roberts, Mario Sopena Novales, John W. Howson
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Publication number: 20250182381Abstract: A graphics processor architecture provides for scan conversion and ray tracing approaches to visible surface determination as concurrent and separate processes. Surfaces can be identified for shading by scan conversion and ray tracing. Data produced by each can be normalized, so that instances of shaders, being executed on a unified shading computation resource, can shade surfaces originating from both ray tracing and rasterization. Such resource also may execute geometry shaders. The shaders can emit rays to be tested for intersection by the ray tracing process. Such shaders can complete, without waiting for those emitted rays to complete. Where scan conversion operates on tiles of 2-D screen pixels, the ray tracing can be tile aware, and controlled to prioritize testing of rays based on scan conversion status. Ray population can be controlled by feedback to any of scan conversion, and shading.Type: ApplicationFiled: February 5, 2025Publication date: June 5, 2025Inventors: John W. Howson, Luke Tilman Peterson, Steven J. Clohset
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Patent number: 12322025Abstract: A method and system for performing a render using a graphics processing unit that implements a tile-based graphics pipeline where a rendering space is sub-divided into tiles. Geometry data for the render is received, the geometry data including primitives associated with one or more vertex shader programs. The geometry data is processed using the vertex shader programs to generate processed primitives, and it is determined in which tile each of the processed primitives are located. For at least one selected tile there is stored i) a representation of per-tile vertex shader data identifying the one or more vertex shader programs used to generate the processed primitives in that tile, and ii) a representation of per-tile render data that can be used when rendering the processed primitives in that tile in subsequent stages of the graphics pipeline.Type: GrantFiled: March 31, 2023Date of Patent: June 3, 2025Assignee: Imagination Technologies LimitedInventors: John W. Howson, Xile Yang, Maurizio Zucchelli
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Publication number: 20250173955Abstract: Methods and primitive block generators for generating primitive blocks in a graphics processing system. The methods include receiving transformed position data for a current primitive, the transformed position data indicating a position of the current primitive in rendering space; determining a distance between the position of the current primitive and a position of a current primitive block based on the transformed position data for the current primitive; determining whether to add the current primitive to the current primitive block based on the distance and a fullness of the current primitive block; in response to determining that the current primitive is to be added to the current primitive block, adding the current primitive to the current primitive block; and in response to determining that the current primitive is not to be added to the current primitive block, flushing the current primitive block and adding the current primitive to a new current primitive block.Type: ApplicationFiled: January 18, 2025Publication date: May 29, 2025Inventors: Xile YANG, Robert BRIGG, John W. HOWSON
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Publication number: 20250166286Abstract: Ray tracing units, processing modules and methods are described for generating one or more reduced acceleration structures to be used for intersection testing in a ray tracing system for processing a 3D scene. Nodes of the reduced acceleration structure(s) are determined, wherein a reduced acceleration structure represents a subset of the 3D scene. The reduced acceleration structure(s) are stored for use in intersection testing. Since the reduced acceleration structures represent a subset of the scene (rather than the whole scene) the memory usage for storing the acceleration structure is reduced, and the latency in the traversal of the acceleration structure is reduced.Type: ApplicationFiled: January 17, 2025Publication date: May 22, 2025Inventors: John W. Howson, Luke T. Peterson