Abstract: A microsequencer includes a memory array (110) which is interfaced with a push/pop register (100). Data is input to the push/pop register (100) through a multiplexer (104) and also to Read register (102). The stack comprised of the RAM (110) and the register (100) can be push or pop with control logic (120). Stack pointer (130) and Read pointer (134) are provided for storing the stack and read pointers. The Read register (102) allows reading of data independent of the contents of the push/pop register (100) and the Read pointer (134) allows independent reading of information in the RAM (110).

Abstract: An n.times.n bit multiplier of a type having input and output registers and associated multiplexers, a multiplier array and adders, a shifter and an accumulator. The multiplier includes a temporary register having an input coupled in parallel with an input of the accumulator to an output of the shifter and an output coupled to a multiplexer for controlling the flow of output data from the temporary register to the multiplier array. The temporary register is responsive to a SELREG control signal to become enabled and disabled. An input of the shifter is coupled to an output of the adder.

Abstract: A novel analog-to-digital converter is integrated on a semiconductor substrate utilizing I.sup.2 L techniques. The resulting converter, which utilizes dual slope integration to generate a digital signal, operates from a single low-voltage power supply and has few external components. The converter is suitable for integration with I.sup.2 L digital circuitry to provide a complete digital system, which operates in accordance with an analog input signal, on a single semiconductor chip.

Abstract: In a dual slope analog-to-digital converter, the conversion cycle is divided into three states; a first state in which the system is initialized by discharging an integration capacitor, a second state in which integration is performed with an analog voltage representing the measured parameter and a third state in which integration is performed with an analog reference voltage representing the full scale of the measured parameter. The duration of each state, derived from a counter, is selected according to the particular application in which the analog-to-digital converter is utilized. In one embodiment, each count is representative of a unit of the parameter being measured or a fraction thereof. The count or value which represents the commencement of the third state has a selected relationship to the minimum value of the measured parameter best suited for the particular application.

Abstract: A novel I.sup.2 L ring oscillator circuit includes means by which the repetition rate is adjustable. A plurality of cascaded logic gate stages are coupled in a ring configuration to achieve a plurality of astable states. Frequency adjustments are made by varying the amount of injection current applied to the logic gates which comprise the ring oscillator. Lowering injection current increases delay time from one astable state to the next resulting in a lower frequency repetition rate. The ring oscillator may be fabricated on a single substrate along with other I.sup.2 L circuitry and be utilized as the clock source therefore. In one embodiment of the circuit, a plurality of discrete frequency adjustments are provided; by selection of a particular lead pattern during fabrication of the oscillator, the appropriate injection current to the oscillator logic gates is provided.