Abstract: A power distribution control system for high speed electronics limits peak transient current when entering or exiting circuitry into or out of a system wide freeze mode. The power distribution control system includes power supply circuitry which provides a first supply voltage on a first output line. Multiple circuitry sections are each coupled to and powered by the power supply circuitry. While in the system wide freeze mode, each of the multiple circuitry sections is held inactive by a corresponding one of multiple control signals. A freeze controller is coupled to each of the circuitry sections, and provides the corresponding control signal to each circuitry section. The control signal provided to each particular circuitry section causes the particular circuitry section to enter or exit the system wide freeze mode independently of others of the multiple circuitry sections.

Abstract: A method of the invention, embodied for example as computer executable instructions stored on a computer readable medium and executed on a personal computer, includes obtaining a first filter profile for an audio conditioning unit of a sound conditioning system. The first filter profile corresponds to an audiogram of a user of the system. Sound data corresponding to audio to be played is obtained and filtered using the first filter profile. The filtered sound data is played for the user of the sound conditioning system. The user can adjust the first filter profile for current hearing capabilities and specific sound environments without the aid of an audiologist. Multiple filter profiles can be uploaded from the personal computer to an audio conditioning unit of a listening conditioning system.

Abstract: A listening conditioning system includes an audio conditioning unit and optionally one or more audio delivery components. A receiver provides at least one receiver channel which receives signals indicative of sound from a source of desired sound, and provides as an output digital sound data for each receiver channel. Digital signal processing circuitry coupled to the at least one receiver channel filters the digital sound data from each receiver channel using a filter profile to obtain filtered digital sound data. A profile upload input is configured to receive a multiple filter profiles, wherein each of the filter profiles corresponds to user preferences or to an audiogram of a user of the listening conditioning system and to a particular sound environment. A profile selection user input can be used to select the filter profile from the multiple filter profiles. A transmitter coupled to the digital signal processing circuitry is configured to transmit filtered sound data from each receiver channel.

Abstract: An improvement in a bus converter that provides a bus to bus address translation function permitting access from an I/O device connected on the I/O bus to a system bus and system memory, where the bus converter includes a circuit connected to the I/O bus to partition I/O addresses received from the I/O bus into a lower order field and a high order field and connected to a circuit to receive DMA ID's from the I/O bus to combine this DMA ID with the high order field to form a first combined address. The first combined address is input to a memory which provides corresponding control field and prefix field data. An address formatter is further included that is connected to receive the control field and prefix field data from the memory and further connected to receive the low order address field. The address formatter forms a second combined address from the prefix field, control field and lower order address field. This second combined address is then provided to a system bus to permit access to the system bus.

Abstract: A method and apparatus are provided to enable interruption of list processing operations in a computer system and to enable restart from the point of interruption. A mechanism, at a predetermined point of the list processing operation, operates to recognize occurrences of interrupting events. If any such events are present, a mechanism saves the status of the list processing operation, saves the identification of the task associated with instruction executing the list processing operation and locks the list or queue. After the interrupt is handled, a mechanism restores status, and unlocks the list or queue only when the identified task is active again and the instruction which had been executing the list processing operation is again executing.

Abstract: Improved task handling apparatus for a computer system where the task dispatcher is selectively operable under instruction control for performing task queue selection and where the intertask communication mechanism can return a task dispatching element (TDE) to a non-prime task dispatching queue (TDQ) as well as to the prime TDQ. Whenever a TDE is returned to the prime TDQ, the task dispatcher makes a pre-emptive task switch. Also, if there are no task dispatching elements on the current non-prime TDQ, the task dispatcher switches to dispatch TDE's from the prime TDQ.

Abstract: Task handling apparatus in a computer system is structured to be common to system control tasks, user tasks and I/O tasks. Although the task handling apparatus contains a task priority structure, all tasks are handled in the same manner, and there are no fixed interrupt levels for I/O tasks. There are N levels of priority, and N is variable. Each task is a server for a functional request. Task dispatching elements (TDE's) are enqueued in priority sequence on a task dispatching queue (TDQ). A task dispatcher functions to dispatch the highest priority TDE on the TDQ, if any, and to perform task switching. Intertask communication is accomplished by send message, send count, receive message and receive count mechanisms, and is coupled with task synchronization. Task synchronization is achieved by dequeueing and enqueueing TDE's on the TDQ. An active task becomes inactive dispatchable when a higher priority TDE is enqueued on the TDQ by send message or send count mechanisms.