Patents by Inventor John W. Medernach

John W. Medernach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5277769
    Abstract: Porous semiconducting material, e.g. silicon, is formed by electrochemical treatment of a specimen in hydrofluoric acid, using the specimen as anode. Before the treatment, the specimen can be masked. The porous material is then etched with a caustic solution or is oxidized, depending of the kind of structure desired, e.g. a thinned specimen, a specimen, a patterned thinned specimen, a specimen with insulated electrical conduits, and so on. Thinned silicon specimen can be subjected to tests, such as measurement of interstitial oxygen by Fourier transform infra-red spectroscopy (FTIR).
    Type: Grant
    Filed: November 27, 1991
    Date of Patent: January 11, 1994
    Assignee: The United States of America as represented by the Department of Energy
    Inventor: John W. Medernach
  • Patent number: 5015346
    Abstract: An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.
    Type: Grant
    Filed: April 10, 1990
    Date of Patent: May 14, 1991
    Assignee: United States Department of Energy
    Inventors: Terry R. Guilinger, Howland D. T. Jones, Michael J. Kelly, John W. Medernach, Joel O. Stevenson, Sylvia S. Tsao
  • Patent number: 4410240
    Abstract: A mounting structure is provided for electro-optical display character elements. The mounting structure includes first and second electrically insulative substrates, each substrate of which includes an aperture. The aperture of the second substrate is somewhat smaller than the aperture of the first substrate such that when the apertures are aligned, the second substrate exhibits a lip under the aperture of the first structure. A display character element including electrodes on the opposed surfaces thereof is situated in the aperture of the first substrate. Electrode elements on the lower surface of the display character element are electrically coupled to corresponding electrode elements situated on the upper surface of the second substrate extending onto the lip. An interconnecting element electrically couples electrodes on the upper surface of the character element to corresponding electrodes on the upper surface of the first substrate.
    Type: Grant
    Filed: July 13, 1981
    Date of Patent: October 18, 1983
    Assignee: Motorola, Inc.
    Inventor: John W. Medernach
  • Patent number: 4371598
    Abstract: A method is provided for fabricating substantially vertically aligned patterns of material on the opposed surfaces of a transparent substrate by employing a single external mask.
    Type: Grant
    Filed: July 6, 1981
    Date of Patent: February 1, 1983
    Assignee: Motorola, Inc.
    Inventors: John W. Medernach, Ivan A. Novak, Harry D. Bush