Patents by Inventor John W. Mosier, II, deceased

John W. Mosier, II, deceased has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High density power device fabrication process using undercut oxide sidewalls
    Patent number: 5648283
    Abstract: A gate power MOSFET on substrate (20) has a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. Layer (430) on surface (28) patterns areas (446) as stripes or a matrix, and protected areas. Undercut sidewalls (444) of thickness (452), with protruding rims (447), contact the sides of layer (434'). Trench (450) in areas (446) has silicon sidewalls aligned to oxide sidewall (447) and extending depthwise through P-body layer (26) to depth (456). Gate oxide (460) is formed on the trench walls and gate polysilicon (462) refills trench (450) to a level (464) near surface (28) demarcated by the undercut sidewall rims (447). Oxide (468) between spacers (444) covers polysilicon (462). Removing layer (430) exposes surface (28') between the sidewalls (444). Source layer (72) is doped atop the body layer (26') and then trenched to form trench (80) having sidewalls aligned to inner side faces of sidewalls (444).
    Type: Grant
    Filed: January 31, 1994
    Date of Patent: July 15, 1997
    Assignee: Advanced Power Technology, Inc.
    Inventors: Dah Wen Tsang, Dumitru Sdrulla, Douglas A. Pike, Jr., Theodore O. Meyer, John W. Mosier, II, deceased