Abstract: A method for modeling a geological domain in a computer system, in which the computer system includes data processing and data storage modules, one or more user input devices and a display device, in which the system first receives data relating to faults within the domain. Then there is created a surface plot for each fault described in the data, each surface plot being extended to divide the domain in two portions, and the surface plots are combined into a fault network containing all faults described in the data and displayed on the display apparatus. The network display is modified in response to user input, including the first step of rotating the display about its horizontal and vertical axes as desired to inspect the same. Then the system receives manual truncation commands and truncates indicated fault portions responsive to the same.

Abstract: In a demand-paged virtual memory system, the pages are arranged in the virtual memory space in groups. In order to translate an address from the virtual address space to a physical memory address space, the virtual group address component is input to a contents addressable memory (767), which outputs a group code (767), and the group code and virtual page address component (768X,Y) are input to a RAM page table (750) which outputs the page address. When the physical memory capacity is substantially smaller than the virtual address space, the CAM provides a large saving in page table size. In the case where the data-elements provide a plural-dimensional representation, for example as in pixel data, the pages include data elements which are contiguous in each of the plural dimensions in order to reduce the amount of page-swapping between the physical memory and a paging memory. The data-elements in the physical memory are accessible in parallel as contiguous patches.

Abstract: A data array processing system comprises a memory system for storing an array of data elements and addressable by a single address, a plural number N of processors (PROC(0)-(15)) capable of processing data elements in parallel, and an address bus. In order to allow parallel access to the memory system where possible, but permit the processors also to access different addresses, each processor is selectable to supply its respective required address (xq, yq) via the address bus to the memory system to access the memory, and each non-selected processor is operable to determine whether it requires access to the address (xq, yq) on the bus, and if so to access the memory system at the same time as the selected processor.