Patents by Inventor John W. Palmour
John W. Palmour has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8119539Abstract: Methods of forming oxide layers on silicon carbide layers are disclosed, including placing a silicon carbide layer in a chamber such as an oxidation furnace tube that is substantially free of metallic impurities, heating an atmosphere of the chamber to a temperature of about 500° C. to about 1300° C., introducing atomic oxygen in the chamber, and flowing the atomic oxygen over a surface of the silicon carbide layer to thereby form an oxide layer on the silicon carbide layer. In some embodiments, introducing atomic includes oxygen providing a source oxide in the chamber and flowing a mixture of nitrogen and oxygen gas over the source oxide. The source oxide may comprise aluminum oxide or another oxide such as manganese oxide. Some methods include forming an oxide layer on a silicon carbide layer and annealing the oxide layer in an atmosphere including atomic oxygen.Type: GrantFiled: July 14, 2009Date of Patent: February 21, 2012Assignee: Cree, Inc.Inventors: Mrinal K. Das, Anant K. Agarwal, John W. Palmour, Dave Grider
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Publication number: 20100009545Abstract: Methods of forming oxide layers on silicon carbide layers are disclosed, including placing a silicon carbide layer in a chamber such as an oxidation furnace tube that is substantially free of metallic impurities, heating an atmosphere of the chamber to a temperature of about 500° C. to about 1300° C., introducing atomic oxygen in the chamber, and flowing the atomic oxygen over a surface of the silicon carbide layer to thereby form an oxide layer on the silicon carbide layer. In some embodiments, introducing atomic includes oxygen providing a source oxide in the chamber and flowing a mixture of nitrogen and oxygen gas over the source oxide. The source oxide may comprise aluminum oxide or another oxide such as manganese oxide. Some methods include forming an oxide layer on a silicon carbide layer and annealing the oxide layer in an atmosphere including atomic oxygen.Type: ApplicationFiled: July 14, 2009Publication date: January 14, 2010Inventors: Mrinal K. Das, Anant K. Agarwal, John W. Palmour, Dave Grider
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Patent number: 7615801Abstract: High voltage silicon carbide (SiC) devices, for example, thyristors, are provided. A first SiC layer having a first conductivity type is provided on a first surface of a voltage blocking SiC substrate having a second conductivity type. A first region of SiC is provided on the first SiC layer and has the second conductivity type. A second region of SiC is provided in the first SiC layer, has the first conductivity type and is adjacent to the first region of SiC. A second SiC layer having the first conductivity type is provided on a second surface of the voltage blocking SiC substrate. A third region of SiC is provided on the second SiC layer and has the second conductivity type. A fourth region of SiC is provided in the second SiC layer, has the first conductivity type and is adjacent to the third region of SiC. First and second contacts are provided on the first and third regions of SiC, respectively. Related methods of fabricating high voltage SiC devices are also provided.Type: GrantFiled: June 23, 2005Date of Patent: November 10, 2009Assignee: Cree, Inc.Inventors: Sei-Hyung Ryu, Jason R. Jenny, Mrinal K. Das, Anant K. Agarwal, John W. Palmour, Hudson McDonald Hobgood
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Patent number: 7572741Abstract: Methods of forming oxide layers on silicon carbide layers are disclosed, including placing a silicon carbide layer in a chamber such as an oxidation furnace tube that is substantially free of metallic impurities, heating an atmosphere of the chamber to a temperature of about 500 ° C. to about 1300 ° C., introducing atomic oxygen in the chamber, and flowing the atomic oxygen over a surface of the silicon carbide layer to thereby form an oxide layer on the silicon carbide layer. In some embodiments, introducing atomic includes oxygen providing a source oxide in the chamber and flowing a mixture of nitrogen and oxygen gas over the source oxide. The source oxide may comprise aluminum oxide or another oxide such as manganese oxide. Some methods include forming an oxide layer on a silicon carbide layer and annealing the oxide layer in an atmosphere including atomic oxygen.Type: GrantFiled: September 16, 2005Date of Patent: August 11, 2009Assignee: Cree, Inc.Inventors: Mrinal K. Das, Anant K. Agarwal, John W. Palmour, Dave Grider
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Publication number: 20090004883Abstract: Methods of forming oxide layers on silicon carbide layers are disclosed, including placing a silicon carbide layer in a chamber such as an oxidation furnace tube that is substantially free of metallic impurities, heating an atmosphere of the chamber to a temperature of about 500° C. to about 1300° C., introducing atomic oxygen in the chamber, and flowing the atomic oxygen over a surface of the silicon carbide layer to thereby form an oxide layer on the silicon carbide layer. In some embodiments, introducing atomic includes oxygen providing a source oxide in the chamber and flowing a mixture of nitrogen and oxygen gas over the source oxide. The source oxide may comprise aluminum oxide or another oxide such as manganese oxide. Some methods include forming an oxide layer on a silicon carbide layer and annealing the oxide layer in an atmosphere including atomic oxygen.Type: ApplicationFiled: September 16, 2005Publication date: January 1, 2009Inventors: Mrinal K. Das, Anant K. Agarwal, John W. Palmour, Dave Grider
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Patent number: 7414268Abstract: Silicon carbide high voltage semiconductor devices and methods of fabricating such devices are provided. The devices include a voltage blocking substrate. Insulated gate bipolar transistors are provided that have a voltage blocking substrate. Planar and beveled edge termination may be provided.Type: GrantFiled: May 18, 2005Date of Patent: August 19, 2008Assignee: Cree, Inc.Inventors: Sei-Hyung Ryu, Jason R. Jenny, Mrinal K. Das, Hudson McDonald Hobgood, Anant K. Agarwal, John W. Palmour
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Patent number: 7391057Abstract: High voltage silicon carbide (SiC) devices, for example, thyristors, are provided. A first SiC layer having a first conductivity type is provided on a first surface of a voltage blocking SiC substrate having a second conductivity type. A first region of SiC is provided on the first SiC layer and has the second conductivity type. A second region of SiC is provided in the first SiC layer. The second region of SiC has the first conductivity type and is adjacent to the first region of SiC. A second SiC layer having the first conductivity type is provided on a second surface, opposite the first surface, of the voltage blocking SiC substrate. First, second and third contacts are provided on the first region of SiC, the second region of SiC and the second SiC layer, respectively. Related methods of fabricating high voltage SiC devices are also provided.Type: GrantFiled: May 18, 2005Date of Patent: June 24, 2008Assignee: Cree, Inc.Inventors: Sei-Hyung Ryu, Jason R. Jenny, Mrinal K. Das, Hudson McDonald Hobgood, Anant K. Agarwal, John W. Palmour
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Patent number: 7135359Abstract: Large area silicon carbide devices, such as light-activated silicon carbide thyristors, having only two terminals are provided. The silicon carbide devices are selectively connected in parallel by a connecting plate. Silicon carbide thyristors are also provided having a portion of the gate region of the silicon carbide thyristors exposed so as to allow light of an energy greater than about 3.25 eV to activate the gate of the thyristor. The silicon carbide thyristors may be symmetric or asymmetrical. A plurality of the silicon carbide thyristors may be formed on a wafer, a portion of a wafer or multiple wafers. Bad cells may be determined and the good cells selectively connected by a connecting plate.Type: GrantFiled: May 14, 2004Date of Patent: November 14, 2006Assignee: Cree, Inc.Inventors: Anant Agarwal, Sei-Hyung Ryu, John W. Palmour
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Patent number: 7067361Abstract: SiC MESFETs are disclosed which utilize a semi-insulating SiC substrate which substantially free of deep-level dopants. Utilization of the semi-insulating substrate may reduce back-gating effects in the MESFETs. Also provided are SiC MESFETs with a two recess gate structure. MESFETS with a selectively doped p-type buffer layer are also provided. Utilization of such a buffer layer may reduce output conductance by a factor of 3 and produce a 3 db increase in power gain over SiC MESFETs with conventional p-type buffer layers. A ground contact may also be provided to the p-type buffer layer and the p-type buffer layer may be made of two p-type layers with the layer formed on the substrate having a higher dopant concentration. SiC MESFETs according to embodiments of the present invention may also utilize chromium as a Schottky gate material. Furthermore, an oxide-nitride-oxide (ONO) passivation layer may be utilized to reduce surface effects in SiC MESFETs.Type: GrantFiled: November 12, 2003Date of Patent: June 27, 2006Assignee: Cree, Inc.Inventors: Scott T. Allen, John W. Palmour, Terrence S. Alcorn
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Patent number: 6998322Abstract: Capacitors and interconnection structures for silicon carbide are provided having an oxide layer, a layer of dielectric material and a second oxide layer on the layer of dielectric material. The thickness of the oxide layers may be from about 0.5 to about 33 percent of the thickness of the oxide layers and the layer of dielectric material. Capacitors and interconnection structures for silicon carbide having silicon oxynitride layer as a dielectric structure are also provided. Such a dielectric structure may be between metal layers to provide a metal-insulator-metal capacitor or may be used as a inter-metal dielectric of an interconnect structure so as to provide devices and structures having improved mean time to failure. Methods of fabricating such capacitors and structures are also provided.Type: GrantFiled: March 6, 2003Date of Patent: February 14, 2006Assignee: Cree, Inc.Inventors: Mrinal Kanti Das, Lori A. Lipkin, John W. Palmour, Scott Sheppard, Helmut Hagleitner
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Patent number: 6972436Abstract: Capacitors and interconnection structures for silicon carbide are provided having an oxide layer, a layer of dielectric material and a second oxide layer on the layer of dielectric material. The thickness of the oxide layers may be from about 0.5 to about 33 percent of the thickness of the oxide layers and the layer of dielectric material. Capacitors and interconnection structures for silicon carbide having silicon oxynitride layer as a dielectric structure are also provided. Such a dielectric structure may be between metal layers to provide a metal-insulator-metal capacitor or may be used as a inter-metal dielectric of an interconnect structure so as to provide devices and structures having improved mean time to failure. Methods of fabricating such capacitors and structures are also provided.Type: GrantFiled: June 11, 2001Date of Patent: December 6, 2005Assignee: Cree, Inc.Inventors: Mrinal Kanti Das, Lori A. Lipkin, John W. Palmour, Scott Sheppard, Helmut Hagleitner
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Patent number: 6956238Abstract: Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) and methods of fabricating silicon carbide MOSFETs are provided. The silicon carbide MOSFETs have an n-type silicon carbide drift layer, spaced apart p-type silicon carbide regions in the n-type silicon carbide drift layer and having n-type silicon carbide regions therein, and a nitrided oxide layer. The MOSFETs also have n-type shorting channels extending from respective ones of the n-type silicon carbide regions through the p-type silicon carbide regions to the n-type silicon carbide drift layer. In further embodiments, silicon carbide MOSFETs and methods of fabricating silicon carbide MOSFETs are provided that include a region that is configured to self-deplete the source region, between the n-type silicon carbide regions and the drift layer, adjacent the oxide layer, upon application of a zero gate bias.Type: GrantFiled: July 24, 2001Date of Patent: October 18, 2005Assignee: Cree, Inc.Inventors: Sei-Hyung Ryu, Anant Agarwal, Mrinal Kanti Das, Lori A. Lipkin, John W. Palmour, Ranbir Singh
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Publication number: 20040206976Abstract: Large area silicon carbide devices, such as light-activated silicon carbide thyristors, having only two terminals are provided. The silicon carbide devices are selectively connected in parallel by a connecting plate. Silicon carbide thyristors are also provided having a portion of the gate region of the silicon carbide thyristors exposed so as to allow light of an energy greater than about 3.25 eV to activate the gate of the thyristor. The silicon carbide thyristors may be symmetric or asymmetrical. A plurality of the silicon carbide thyristors may be formed on a wafer, a portion of a wafer or multiple wafers. Bad cells may be determined and the good cells selectively connected by a connecting plate.Type: ApplicationFiled: May 14, 2004Publication date: October 21, 2004Inventors: Anant Agarwal, Sei-Hyung Ryu, John W. Palmour
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Publication number: 20040159865Abstract: SiC MESFETs are disclosed which utilize a semi-insulating SiC substrate which substantially free of deep-level dopants. Utilization of the semi-insulating substrate may reduce back-gating effects in the MESFETs. Also provided are SiC MESFETs with a two recess gate structure. MESFETS with a selectively doped p-type buffer layer are also provided. Utilization of such a buffer layer may reduce output conductance by a factor of 3 and produce a 3 db increase in power gain over SiC MESFETs with conventional p-type buffer layers. A ground contact may also be provided to the p-type buffer layer and the p-type buffer layer may be made of two p-type layers with the layer formed on the substrate having a higher dopant concentration. SiC MESFETs according to embodiments of the present invention may also utilize chromium as a Schottky gate material. Furthermore, an oxide-nitride-oxide (ONO) passivation layer may be utilized to reduce surface effects in SiC MESFETs.Type: ApplicationFiled: November 12, 2003Publication date: August 19, 2004Inventors: Scott T. Allen, John W. Palmour, Terrence S. Alcorn
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Patent number: 6770911Abstract: Large area silicon carbide devices, such as light-activated silicon carbide thyristors, having only two terminals are provided. The silicon carbide devices are selectively connected in parallel by a connecting plate. Silicon carbide thyristors are also provided having a portion of the gate region of the silicon carbide thyristors exposed so as to allow light of an energy greater than about 3.25 eV to activate the gate of the thyristor. The silicon carbide thyristors may be symmetric or asymmetrical. A plurality of the silicon carbide thyristors may be formed on a wafer, a portion of a wafer or multiple wafers. Bad cells may be determined and the good cells selectively connected by a connecting plate.Type: GrantFiled: September 12, 2001Date of Patent: August 3, 2004Assignee: Cree, Inc.Inventors: Anant Agarwal, Sei-Hyung Ryu, John W. Palmour
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Patent number: 6767843Abstract: Methods for fabricating a layer of oxide on a silicon carbide layer are provided by forming the oxide layer on the silicon carbide layer by oxidizing the silicon carbide layer in an N2O environment. A predetermined temperature profile and/or a predetermined flow rate profile of N2O are provided during the oxidation. The predetermined temperature profile and/or predetermined flow rate profile may be constant or variable and may include ramps to steady state conditions. The predetermined temperature profile and/or the predetermined flow rate profile are selected so as to reduce interface states of the oxide/silicon carbide interface with energies near the conduction band of SiC.Type: GrantFiled: October 1, 2001Date of Patent: July 27, 2004Assignee: Cree, Inc.Inventors: Lori A. Lipkin, Mrinal Kanti Das, John W. Palmour
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Patent number: 6686616Abstract: SiC MESFETs are disclosed which utilize a semi-insulating SiC substrate which substantially free of deep-level dopants. Utilization of the semi-insulating substrate may reduce back-gating effects in the MESFETs. Also provided are SiC MESFETs with a two recess gate structure. MESFETS with a selectively doped p-type buffer layer are also provided. Utilization of such a buffer layer may reduce output conductance by a factor of 3 and produce a 3 db increase in power gain over SiC MESFETs with conventional p-type buffer layers. A ground contact may also be provided to the p-type buffer layer and the p-type buffer layer may be made of two p-type layers with the layer formed on the substrate having a higher dopant concentration. SiC MESFETs according to embodiments of the present invention may also utilize chromium as a Schottky gate material. Furthermore, an oxide-nitride-oxide (ONO) passivation layer may be utilized to reduce surface effects in SiC MESFETs.Type: GrantFiled: May 10, 2000Date of Patent: February 3, 2004Assignee: Cree, Inc.Inventors: Scott T. Allen, John W. Palmour, Terrence S. Alcorn
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Publication number: 20030160274Abstract: Capacitors and interconnection structures for silicon carbide are provided having an oxide layer, a layer of dielectric material and a second oxide layer on the layer of dielectric material. The thickness of the oxide layers may be from about 0.5 to about 33 percent of the thickness of the oxide layers and the layer of dielectric material. Capacitors and interconnection structures for silicon carbide having silicon oxynitride layer as a dielectric structure are also provided. Such a dielectric structure may be between metal layers to provide a metal-insulator-metal capacitor or may be used as a inter-metal dielectric of an interconnect structure so as to provide devices and structures having improved mean time to failure. Methods of fabricating such capacitors and structures are also provided.Type: ApplicationFiled: March 6, 2003Publication date: August 28, 2003Inventors: Mrinal Kanti Das, Lori A. Lipkin, John W. Palmour, Scott Sheppard, Helmut Hagleitner
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Publication number: 20030047748Abstract: Large area silicon carbide devices, such as light-activated silicon carbide thyristors, having only two terminals are provided. The silicon carbide devices are selectively connected in parallel by a connecting plate. Silicon carbide thyristors are also provided having a portion of the gate region of the silicon carbide thyristors exposed so as to allow light of an energy greater than about 3.25 eV to activate the gate of the thyristor. The silicon carbide thyristors may be symmetric or asymmetrical. A plurality of the silicon carbide thyristors may be formed on a wafer, a portion of a wafer or multiple wafers. Bad cells may be determined and the good cells selectively connected by a connecting plate.Type: ApplicationFiled: September 12, 2001Publication date: March 13, 2003Inventors: Anant Agarwal, Sei-Hyung Ryu, John W. Palmour
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Patent number: 6514779Abstract: A silicon carbide device is fabricated by forming a plurality of a same type of silicon carbide devices on at least a portion of a silicon carbide wafer in a predefined pattern. The silicon carbide devices have corresponding first contacts on a first face of the silicon carbide wafer. The plurality of silicon carbide devices are electrically, tested to identify ones of the plurality of silicon carbide devices which pass an electrical test. The first contact of the identified ones of the silicon carbide devices are then selectively interconnected. Devices having a plurality of selectively connected silicon carbide devices of the same type are also provided.Type: GrantFiled: October 17, 2001Date of Patent: February 4, 2003Assignee: Cree, Inc.Inventors: Sei-Hyung Ryu, Anant Agarwal, Craig Capell, John W. Palmour