Abstract: A PLL fail-over circuit technique and method to mitigate the effects of single-event transients comprises providing a pair of substantially identical phase-locked loops and producing a respective delayed clock signal from each. The outputs of the phase-locked loops are monitored for errors comprising high frequency transients or differences in clock signal outputs from a reference frequency. A clock out signal is output representative of the first delayed clock signal if an error is detected in the second phase-locked loop and the second delayed clock signal is output if an error is detected in the first phase-locked loop.

Abstract: A PLL fail-over circuit technique and method to mitigate the effects of single-event transients comprises providing a pair of substantially identical phase-locked loops and producing a respective delayed clock signal from each. The outputs of the phase-locked loops are monitored for errors comprising high frequency transients or differences in clock signal outputs from a reference frequency. A clock out signal is output representative of the first delayed clock signal if an error is detected in the second phase-locked loop and the second delayed clock signal is output if an error is detected in the first phase-locked loop.

Abstract: The amount of data transmitted in a primary data channel is increased by modulating a reference clock signal of the primary data channel with secondary data to form a separate secondary data channel. Primary data is formed into a primary data signal using the modulated reference clock signal, and a transmitter transmits the primary data signal to a receiver. The receiver recovers the primary data and modulated reference clock signal from the primary data signal, and then recovers the secondary data from the recovered modulated reference clock signal.