Patents by Inventor John W. Regnier

John W. Regnier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method to facilitate hierarchical netlist checking
    Patent number: 7805694
    Abstract: An apparatus and method are disclosed which determine locations where verification data should exist in a circuit representation and then propagates verification or circuit properties within a circuit representation. For a hierarchical representation of a circuit, a minimum number of modified circuit entities are created and added to the hierarchical representation such that pertinent critical net and property information is represented at each hierarchical level.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: September 28, 2010
    Assignee: Micron Technology, Inc.
    Inventor: John W. Regnier
  • Apparatus and method to facilitate hierarchical netlist checking
    Patent number: 7240316
    Abstract: An apparatus and method are disclosed which determine locations where verification data should exist in a circuit representation and then propagates verification or circuit properties within a circuit representation. For a hierarchical representation of a circuit, a minimum number of modified circuit entities are created and added to the hierarchical representation such that pertinent critical net and property information is represented at each hierarchical level.
    Type: Grant
    Filed: April 16, 2002
    Date of Patent: July 3, 2007
    Assignee: Micron Technology, Inc.
    Inventor: John W. Regnier
  • Fast algorithm to extract flat information from hierarchical netlists
    Patent number: 6886140
    Abstract: The present invention provides a method and apparatus which extracts flat data from a hierarchically related representation of a circuit, such as a netlist. The apparatus and method identifies unique cell elements by a cell instance identifier and determines flat data associated with those elements. When a previously encountered cell instance which has flat data stored describing that element is selected, higher level flat data which has been stored as the apparatus traverses the representation is appended to the stored flat data for the selected element. In this manner, an optimum flat data path to all elements, nets and components is created without a need for re-scanning previously encountered cell instances.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: April 26, 2005
    Assignee: Micron Technology, Inc.
    Inventor: John W. Regnier
  • Apparatus and method to facilitate hierarchical netlist checking
    Publication number: 20030208721
    Abstract: An apparatus and method are disclosed which determine locations where verification data should exist in a circuit representation and then propagates verification or circuit properties within a circuit representation. For a hierarchical representation of a circuit, a minimum number of modified circuit entities are created and added to the hierarchical representation such that pertinent critical net and property information is represented at each hierarchical level.
    Type: Application
    Filed: April 16, 2002
    Publication date: November 6, 2003
    Inventor: John W. Regnier
  • Fast algorithm to extract flat information from hierarchical netlists
    Publication number: 20030139842
    Abstract: The present invention provides a method and apparatus which extracts flat data from a hierarchically related representation of a circuit, such as a netlist. The apparatus and method identifies unique cell elements by a cell instance identifier and determines flat data associated with those elements. When a previously encountered cell instance which has flat data stored describing that element is selected, higher level flat data which has been stored as the apparatus traverses the representation is appended to the stored flat data for the selected element. In this manner, an optimum flat data path to all elements, nets and components is created without a need for re-scanning previously encountered cell instances.
    Type: Application
    Filed: January 17, 2002
    Publication date: July 24, 2003
    Applicant: Micron Technology, Inc.
    Inventor: John W. Regnier