Abstract: Apparatus, systems, and methods for providing high voltage to memory devices are provided. One apparatus includes a low voltage input and a two-rail level shifting. The two-rail level shifting is configured to increase the low voltage or to decrease the low voltage to an amount that is less than or equal to a ground potential based on the amount of the low voltage. A system includes a low voltage input for receiving a voltage and a two-rail level shifting coupled to the low voltage input. The two-rail level shifting is configured to increase the voltage to a positive voltage if the voltage is equal to a ground potential and decrease the voltage to a negative voltage if the voltage is greater than the ground potential. One method includes receiving a voltage, modifying the voltage to generate one of a plurality of output voltages, and providing the output voltage to a memory device.

Abstract: A method and apparatus to program data into a row of a non-volatile memory array and verify, internally to the non-volatile memory array, that the data was successfully programmed. The verification includes comparing the programmed data from the row of the non-volatile memory array to data in the plurality of high voltage page latches that were used to program the row.

Abstract: Apparatus, systems, and methods for providing high voltage to memory devices are provided. One apparatus includes a low voltage input and a two-rail level shifting. The two-rail level shifting is configured to increase the low voltage or to decrease the low voltage to an amount that is less than or equal to a ground potential based on the amount of the low voltage. A system includes a low voltage input for receiving a voltage and a two-rail level shifting coupled to the low voltage input. The two-rail level shifting is configured to increase the voltage to a positive voltage if the voltage is equal to a ground potential and decrease the voltage to a negative voltage if the voltage is greater than the ground potential. One method includes receiving a voltage, modifying the voltage to generate one of a plurality of output voltages, and providing the output voltage to a memory device.

Abstract: A method for fabricating a magnetic random access memory circuit (MRAM) and a MRAM circuit resulting therefrom are provided. The method includes depositing a first conductive layer upon and in contact with a plurality of magnetic cell junctions and selectively removing portions of the first conductive layer arranged above the plurality of magnetic cell junctions. In addition, the method includes depositing a second conductive layer above remaining portions of the first conductive layer and the plurality of magnetic cell junctions. The resulting circuit may include a field-inducing line having thickness and/or width variations relative to underlying magnetic cell junctions.

Abstract: A charge pump circuit includes a first capacitor having an input coupled to a first signal. A second capacitor has an input coupled to a second signal. A first diode has an anode coupled to an output of the first capacitor and a cathode coupled to an output of the second capacitor. A second diode has an anode coupled to the output of the second capacitor and a cathode coupled to the output of the first capacitor. A controllable switch has a control input coupled to the output of the second capacitor and couples the output of the first capacitor to an output of the charge pump circuit.

Abstract: One embodiment of the differential sense amplifier of the present includes a pair of amplifier portions, each of which includes a reference branch and an amplifying branch. Each amplifier portion amplifies one input signal of the differential input signal applied to the differential sense amplifier by an amount related to the difference between the applied input signal and a reference signal established by the reference branch of the amplifier portion. The input signals are cross-coupled between the amplifier portions so that each input signal is applied to the reference branch of one amplifier portion and to the amplifying branch of the other amplifier portion. Separate reference nodes and reference signals are established for each amplifier portion. A change in the differential input signal creates correspondingly opposite changes in the magnitude of the reference signal and the input signal applied to the amplifying branch of both amplifier portions to provide greater gain and sensitivity.

Abstract: A current mirror sense amplifier includes current control devices connected in series with each pair of transistors forming a reference branch and an amplifying branch of the amplifier. The control devices are connected and biased in a cross latched manner, and when the reference and amplifying branches respond to a differential input signal, the conductivity of the control devices regeneratively changes until the current through both branches is ultimately terminated and the output signal attains a level substantially at the level of one of the supply voltages, Vcc and Vss. The sense amplifier also includes resetting devices for reestablishing the initial conductivity states of the branches and the control devices, in order to allow the sense amplifier to respond to a new differential input signal. Biasing transistors establish initial bias levels for the control devices which prevent them from regenerating into the opposite conductive until a differential input signal is applied.