Abstract: Some implementations can include a desiccant breather having an inner pipe having a top portion with a lip extending radially from the inner pipe, the inner pipe having a threaded portion and a top connector. The desiccant breather can also include an outer pipe having a diameter sufficient to accommodate the inner pipe, the outer pipe having a bottom connector and a cap. The desiccant breather can further include a desiccant breather body portion having a cavity configured to hold desiccant material. The lip of the inner pipe can have a diameter equal to or greater than a diameter of the outer pipe.

Abstract: Some implementations can include a desiccant breather having an inner pipe having a top portion with a lip extending radially from the inner pipe, the inner pipe having a threaded portion and a top connector. The desiccant breather can also include an outer pipe having a diameter sufficient to accommodate the inner pipe, the outer pipe having a bottom connector and a cap. The desiccant breather can further include a desiccant breather body portion having a cavity configured to hold desiccant material. The lip of the inner pipe can have a diameter equal to or greater than a diameter of the outer pipe.

Abstract: Some implementations can include a desiccant breather having an inner pipe having a top portion with a lip extending radially from the inner pipe, the inner pipe having a threaded portion and a top connector. The desiccant breather can also include an outer pipe having a diameter sufficient to accommodate the inner pipe, the outer pipe having a bottom connector and a cap. The desiccant breather can further include a desiccant breather body portion having a cavity configured to hold desiccant material. The lip of the inner pipe can have a diameter equal to or greater than a diameter of the outer pipe.

Abstract: Some implementations can include a desiccant breather having an inner pipe having a top portion with a lip extending radially from the inner pipe, the inner pipe having a threaded portion and a top connector. The desiccant breather can also include an outer pipe having a diameter sufficient to accommodate the inner pipe, the outer pipe having a bottom connector and a cap. The desiccant breather can further include a desiccant breather body portion having a cavity configured to hold desiccant material. The lip of the inner pipe can have a diameter equal to or greater than a diameter of the outer pipe.

Abstract: A computer system assigns a particular counter from among a plurality of counters currently in a counter free pool to count a number of mappings of logical registers from among a plurality of logical registers to a particular physical register from among a plurality of physical registers, responsive to an execution of an instruction by a mapper unit mapping at least one logical register from among the plurality of logical registers to the particular physical register, wherein the number of the plurality of counters is less than a number of the plurality of physical registers. The computer system, responsive to the counted number of mappings of logical registers to the particular physical register decremented to less than a minimum value, returns the particular counter to the counter free pool.

Abstract: A computer system assigns a particular counter from among a plurality of counters currently in a counter free pool to count a number of mappings of logical registers from among a plurality of logical registers to a particular physical register from among a plurality of physical registers, responsive to an execution of an instruction by a mapper unit mapping at least one logical register from among the plurality of logical registers to the particular physical register, wherein the number of the plurality of counters is less than a number of the plurality of physical registers. The computer system, responsive to the counted number of mappings of logical registers to the particular physical register decremented to less than a minimum value, returns the particular counter to the counter free pool.

Abstract: A hydrocarbon conversion catalyst comprising a modified beta zeolite, an amorphous inorganic oxide and a hydrogenation component wherein the said catalyst support has an NH3-AI of less than 3.5 and/or an IEC-AI of less than 3.7.

Abstract: A computer system assigns a particular counter from among a plurality of counters currently in a counter free pool to count a number of mappings of logical registers from among a plurality of logical registers to a particular physical register from among a plurality of physical registers, responsive to an execution of an instruction by a mapper unit mapping at least one logical register from among the plurality of logical registers to the particular physical register, wherein the number of the plurality of counters is less than a number of the plurality of physical registers. The computer system, responsive to the counted number of mappings of logical registers to the particular physical register decremented to less than a minimum value, returns the particular counter to the counter free pool.

Abstract: A mapper unit of an out-of-order processor assigns a particular counter currently in a counter free pool to count a number of mappings of logical registers to a particular physical register from among multiple physical registers, responsive to an execution of an instruction by the mapper unit mapping at least one logical register to the particular physical register. The number of counters is less than the number of physical registers. The mapper unit, responsive to the counted number of mappings of logical registers to the particular physical register decremented to less than a minimum value, returns the particular counter to the counter free pool.

Abstract: A computer system assigns a particular counter from among a plurality of counters currently in a counter free pool to count a number of mappings of logical registers from among a plurality of logical registers to a particular physical register from among a plurality of physical registers, responsive to an execution of an instruction by a mapper unit mapping at least one logical register from among the plurality of logical registers to the particular physical register, wherein the number of the plurality of counters is less than a number of the plurality of physical registers. The computer system, responsive to the counted number of mappings of logical registers to the particular physical register decremented to less than a minimum value, returns the particular counter to the counter free pool.

Abstract: A mapper unit of an out-of-order processor assigns a particular counter currently in a counter free pool to count a number of mappings of logical registers to a particular physical register from among multiple physical registers, responsive to an execution of an instruction by the mapper unit mapping at least one logical register to the particular physical register. The number of counters is less than the number of physical registers. The mapper unit, responsive to the counted number of mappings of logical registers to the particular physical register decremented to less than a minimum value, returns the particular counter to the counter free pool.

Abstract: A branch prediction algorithm is used to generate a prediction of whether or not a branch will be taken. One or more instructions are fetched such that, for each of the fetched instructions, the prediction initiates a fetch of an instruction at a predicted target of the branch. A test is performed to ascertain whether or not the prediction was generated late relative to the fetched instructions, so that if the branch is later detected as mispredicted, that detection can be correlated to the late prediction. When the prediction is generated late relative to the fetched instructions, a latent prediction is selected by utilizing a fetching initiated by the latent prediction such that a new fetch is not started.

Abstract: A dual-issue instruction is decoded to determine a plurality of LSU dependencies needed by an LSU part of the dual-issue instruction and a plurality of non-LSU dependencies needed by a non-LSU part of the dual-issue instruction. During dispatch of the dual-issue instruction by the microprocessor, the dual dependency matrices are employed as follows: a Load-Store Unit (LSU) dependency matrix is written with the plurality of LSU dependencies and a non-LSU dependency matrix is written with the plurality of non-LSU dependencies; an LSU issue valid (LSU IV) indicator is set as valid to issue; an LSU portion of the dual-issue instruction is issued once the plurality of LSU dependencies of the dual issue instruction are satisfied; a non-LSU issue valid (non-LSU IV) indicator is set as valid to issue; and a non-LSU portion of the dual-issue instruction is issued once the plurality of non-LSU dependencies of the dual issue instruction are satisfied.

Abstract: A process for hydrocracking a hydrocarbon feedstock comprising components boiling above 343° C. into a middle distillate fraction in the presence of hydrogen under hydrocracking conditions, comprising contacting the hydrocarbon feedstock in a first hydrocracking zone in the presence of one or more hydrocracking catalysts and thereafter in a second hydrocracking zone in the presence of one or more hydrocracking catalysts, and recovering a middle distillate product, wherein the entire effluent from the first hydrocracking zone is passed into the second hydrocracking zone, and at least one hydrocracking catalyst in the first hydrocracking zone comprises one or more hydrogenation components on a support comprising at least one large pore zeolite having a pore diameter in the range of 0.7-1.

Abstract: A dual-issue instruction is decoded to determine a plurality of LSU dependencies needed by an LSU part of the dual-issue instruction and a plurality of non-LSU dependencies needed by a non-LSU part of the dual-issue instruction. During dispatch of the dual-issue instruction by the microprocessor, the dual dependency matrices are employed as follows: a Load-Store Unit (LSU) dependency matrix is written with the plurality of LSU dependencies and a non-LSU dependency matrix is written with the plurality of non-LSU dependencies; an LSU issue valid (LSU IV) indicator is set as valid to issue; an LSU portion of the dual-issue instruction is issued once the plurality of LSU dependencies of the dual issue instruction are satisfied; a non-LSU issue valid (non-LSU IV) indicator is set as valid to issue; and a non-LSU portion of the dual-issue instruction is issued once the plurality of non-LSU dependencies of the dual issue instruction are satisfied.

Abstract: A process for hydrocracking a hydrocarbonaceous feedstock into a middle distillate utilising a hydrocarbon conversion catalyst comprising a modified beta zeolite and a modified Y zeolite, an amorphous inorganic oxide and a hydrogenation component, wherein the said middle distillate is characterised by having a low aromatics content and/or a low pour point.

Abstract: A method, system, and computer program product for minimizing branch prediction latency in a pipelined computer processing environment are provided. The method includes detecting a branch loop utilizing branch instruction addresses and corresponding target addresses stored in a branch target buffer (BTB). The method also includes fetching the branch loop into a pre-decode instruction buffer and qualifying the branch loop for loop lockdown. The method further includes locking an instruction stream that forms the branch loop in the pre-decode instruction buffer and processing qualified branch loop instructions from the buffer and powering down instruction fetching and branch prediction logic (BPL) associated with the BTB.

Abstract: A branch prediction algorithm is used to generate a prediction of whether or not a branch will be taken. One or more instructions are fetched such that, for each of the fetched instructions, the prediction initiates a fetch of an instruction at a predicted target of the branch. A test is performed to ascertain whether or not the prediction was generated late relative to the fetched instructions, so that if the branch is later detected as mispredicted, that detection can be correlated to the late prediction. When the prediction is generated late relative to the fetched instructions, a latent prediction is selected by utilizing a fetching initiated by the latent prediction such that a new fetch is not started.

Abstract: A microprocessor error detection method, includes providing a primary dependency matrix, providing an issue logic for issuing a micro-op, providing a secondary dependency matrix comprising a copy of the primary dependency matrix, providing a results available vector, the results available vector including an entry for each dependency tracked, receiving an indication from issue logic that it is issuing a micro-op, reading the secondary dependency matrix row corresponding to the issued micro-op, checking if the micro-op being read is dependent on a tracked dependency that is not satisfied by determining if any bit set in the row read from the secondary dependency matrix is not set in the secondary results available vector, and receiving an indication from the issue logic if the micro-op has been rescinded.

Abstract: The processing of instructions from multiple threads using a shared dispatch pipeline is controlled by invoking a dispatch flush operation wherein instructions of a selected thread in the shared dispatch pipeline are flushed in response to resource requirements. A first thread in an SMT may be using more processing than corresponds to its priority because its instructions are dominating use of a shared resource. In this case, to rebalance instruction dispatch between the first thread and the second thread, a dispatch flush of instructions of the first thread is issued. Normally the flushed instructions of a thread are refetched and reenter the dispatch pipeline. If the first thread is dominating use of shared resources, hold may be issued following the dispatch flush holding instructions of the first thread until a balanced utilization is realized.