Abstract: Embodiments of the invention include a method for categorizing and displaying design rule errors. The method may include receiving, from a design rule checker, more than one violation of a design rule within a design layout. The method may also include determining distinct categories of the design rule violations by comparing parameters associated with the design rule violations.

Abstract: Embodiments of the invention include a method for categorizing and displaying design rule errors. The method may include receiving, from a design rule checker, more than one violation of a design rule within a design layout. The method may also include determining distinct categories of the design rule violations by comparing parameters associated with the design rule violations.

Abstract: A computer implemented method, system, and/or computer program product reduce noise in a circuit. A level of noise imposed by an aggressor line on a victim line is determined. The aggressor line and the victim line are an aggressor/victim line pair from multiple aggressor/victim line pairs in a circuit. Determination of the noise level is conducted during a predetermined window of time during which a signal is being transmitted along the aggressor line. Each of the multiple aggressor/victim line pairs are ranked according to a level of noise being imposed by each aggressor line on each victim line. The spacing between a highest ranked aggressor/victim line pair is then expanded.

Abstract: In a method of routing a wire to a shape in an integrated circuit for minimizing undesirable jog creation during a masking process, a plurality of possible placements of the wire relative to a selected edge of the shape resulting in the wire being connected to the shape are determined. A cost is assigned to each placement, the cost indicating an amount of jog that would be created in the masking process corresponding to the placement, wherein a greater cost indicates that a greater jog would be created in the masking process than would be created by a placement assigned a lesser cost. A placement having a lowest cost of the plurality of possible placements is selected.

Abstract: In a method of routing a wire to a shape in an integrated circuit for minimizing undesirable jog creation during a masking process, a plurality of possible placements of the wire relative to a selected edge of the shape resulting in the wire being connected to the shape are determined. A cost is assigned to each placement, the cost indicating an amount of jog that would be created in the masking process corresponding to the placement, wherein a greater cost indicates that a greater jog would be created in the masking process than would be created by a placement assigned a lesser cost. A placement having a lowest cost of the plurality of possible placements is selected.

Abstract: A method for automatic wire size modification comprising the steps of routing a wire to a source; detecting a first size differential between the wire and the source by calculating a width difference between a width of the wire and a width of the source, and dividing the width difference by the width of the wire; and modifying a size of the wire if the first size differential is less than a maximum width percentage and if a length of the source is less than a length range specified by a user.

Abstract: A method for automatic wire size modification comprising the steps of routing a wire to a source; detecting a first size differential between the wire and the source by calculating a first width difference between a length of the wire and a width of the source, and dividing the first width difference by the width of the source; detecting a second size differential between the wire and the source if the first size differential is less than a maximum length percentage by calculating a second width difference between the width of the source and a width of the wire, and dividing the second width difference by the width of the source; and modifying a size of the wire if the second size differential is less than a maximum width percentage.

Abstract: A computer program product stored on machine readable media includes machine executable instructions for displaying a layout of a circuit design, the product including instructions for: over a plurality of layers within a design, identifying at least one of a derived level and a device defined within the plurality; and displaying the at least one derived level and device to a user.

Abstract: A method, apparatus and program product oversee and coordinate the automatic generation, monitoring and submission of package files and other modeling processes to enable focused, flexible and efficient modeling of design performance characteristics.

Abstract: A method, apparatus and program product generate package files that are separately stored and selectively combined to generate a net file suited for system simulation and analysis. Selective combination of the package files using respective reference connections of each package enables focused and efficient modeling of design performance characteristics.