Abstract: A matcher circuit for comparing two binary signals which are presented to two separate units is disclosed. The matcher circuit comprises two half matchers, one in each unit. Each half matcher circuit detects one of the two possible mismatch conditions. The two half matcher circuits are connected by a single wire which is connected to the output of a gate in each half matcher such that the wire is a tied collector AND gate thereby allowing bidirectional information flow on the wire.

Abstract: A high-capacity, low-blocking time-division switching system including a three-stage space-division network is disclosed. In order to achieve high capacity and low blocking the space-division network is physically large resulting in delays of the Pulse Code Modulated (PCM) data words transmitted therethrough which are large in comparison to the individual time slots. In order to effectively increase the time available for the transmission of data words through the space-division network, communication paths through the individual network stages are completed in sequence and overlapped in time. The result of this operation is that a path through each network stage is completed for a time less than or equal to a time slot but the time between establishing the first stage path and removing the last stage path is sufficient to pass an entire data word.